e0e53dee69
Recent git versions now warn about those and they've always been a bit of an annoyance. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
133 lines
3.4 KiB
C
133 lines
3.4 KiB
C
/*
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* This file define the irq handler for MSP SLM subsystem interrupts.
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*
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* Copyright 2005-2007 PMC-Sierra, Inc, derived from irq_cpu.c
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* Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <asm/system.h>
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#include <msp_cic_int.h>
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#include <msp_regs.h>
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/*
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* NOTE: We are only enabling support for VPE0 right now.
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*/
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static inline void unmask_msp_cic_irq(unsigned int irq)
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{
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/* check for PER interrupt range */
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if (irq < MSP_PER_INTBASE)
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*CIC_VPE0_MSK_REG |= (1 << (irq - MSP_CIC_INTBASE));
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else
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*PER_INT_MSK_REG |= (1 << (irq - MSP_PER_INTBASE));
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}
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static inline void mask_msp_cic_irq(unsigned int irq)
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{
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/* check for PER interrupt range */
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if (irq < MSP_PER_INTBASE)
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*CIC_VPE0_MSK_REG &= ~(1 << (irq - MSP_CIC_INTBASE));
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else
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*PER_INT_MSK_REG &= ~(1 << (irq - MSP_PER_INTBASE));
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}
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/*
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* While we ack the interrupt interrupts are disabled and thus we don't need
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* to deal with concurrency issues. Same for msp_cic_irq_end.
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*/
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static inline void ack_msp_cic_irq(unsigned int irq)
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{
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mask_msp_cic_irq(irq);
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/*
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* only really necessary for 18, 16-14 and sometimes 3:0 (since
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* these can be edge sensitive) but it doesn't hurt for the others.
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*/
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/* check for PER interrupt range */
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if (irq < MSP_PER_INTBASE)
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*CIC_STS_REG = (1 << (irq - MSP_CIC_INTBASE));
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else
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*PER_INT_STS_REG = (1 << (irq - MSP_PER_INTBASE));
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}
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static struct irq_chip msp_cic_irq_controller = {
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.name = "MSP_CIC",
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.ack = ack_msp_cic_irq,
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.mask = ack_msp_cic_irq,
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.mask_ack = ack_msp_cic_irq,
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.unmask = unmask_msp_cic_irq,
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};
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void __init msp_cic_irq_init(void)
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{
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int i;
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/* Mask/clear interrupts. */
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*CIC_VPE0_MSK_REG = 0x00000000;
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*PER_INT_MSK_REG = 0x00000000;
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*CIC_STS_REG = 0xFFFFFFFF;
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*PER_INT_STS_REG = 0xFFFFFFFF;
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#if defined(CONFIG_PMC_MSP7120_GW) || \
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defined(CONFIG_PMC_MSP7120_EVAL)
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/*
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* The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
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* These inputs map to EXT_INT_POL[6:4] inside the CIC.
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* They are to be active low, level sensitive.
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*/
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*CIC_EXT_CFG_REG &= 0xFFFF8F8F;
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#endif
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/* initialize all the IRQ descriptors */
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for (i = MSP_CIC_INTBASE; i < MSP_PER_INTBASE + 32; i++)
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set_irq_chip_and_handler(i, &msp_cic_irq_controller,
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handle_level_irq);
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}
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void msp_cic_irq_dispatch(void)
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{
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u32 pending;
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int intbase;
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intbase = MSP_CIC_INTBASE;
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pending = *CIC_STS_REG & *CIC_VPE0_MSK_REG;
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/* check for PER interrupt */
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if (pending == (1 << (MSP_INT_PER - MSP_CIC_INTBASE))) {
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intbase = MSP_PER_INTBASE;
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pending = *PER_INT_STS_REG & *PER_INT_MSK_REG;
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}
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/* check for spurious interrupt */
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if (pending == 0x00000000) {
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printk(KERN_ERR
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"Spurious %s interrupt? status %08x, mask %08x\n",
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(intbase == MSP_CIC_INTBASE) ? "CIC" : "PER",
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(intbase == MSP_CIC_INTBASE) ?
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*CIC_STS_REG : *PER_INT_STS_REG,
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(intbase == MSP_CIC_INTBASE) ?
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*CIC_VPE0_MSK_REG : *PER_INT_MSK_REG);
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return;
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}
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/* check for the timer and dispatch it first */
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if ((intbase == MSP_CIC_INTBASE) &&
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(pending & (1 << (MSP_INT_VPE0_TIMER - MSP_CIC_INTBASE))))
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do_IRQ(MSP_INT_VPE0_TIMER);
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else
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do_IRQ(ffs(pending) + intbase - 1);
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}
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