3cdd54417d
Some headers have used (now) wrong names or havn't had protection at all. This is needed before adding static inline functions to the headers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Magnus Lilja <lilja.magnus@gmail.com> Cc: Holger Schurig <hs4233@mail.mn-solutions.de> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Daniel Mack <daniel@caiaq.de>
210 lines
7.3 KiB
C
210 lines
7.3 KiB
C
#ifndef __MACH_MX35_H__
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#define __MACH_MX35_H__
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/*
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* IRAM
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*/
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#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
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#define MX35_IRAM_SIZE SZ_128K
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#define MX35_L2CC_BASE_ADDR 0x30000000
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#define MX35_L2CC_SIZE SZ_1M
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#define MX35_AIPS1_BASE_ADDR 0x43f00000
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#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
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#define MX35_AIPS1_SIZE SZ_1M
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#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
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#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
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#define MX35_CLKCTL_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x0c000)
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#define MX35_ETB_SLOT4_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x10000)
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#define MX35_ETB_SLOT5_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x14000)
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#define MX35_ECT_CTIO_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x18000)
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#define MX35_I2C_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x80000)
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#define MX35_I2C3_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x84000)
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#define MX35_UART1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x90000)
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#define MX35_UART2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x94000)
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#define MX35_I2C2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x98000)
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#define MX35_OWIRE_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x9c000)
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#define MX35_SSI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa0000)
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#define MX35_CSPI1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa4000)
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#define MX35_KPP_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xa8000)
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#define MX35_IOMUXC_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xac000)
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#define MX35_ECT_IP1_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xb8000)
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#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
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#define MX35_SPBA0_BASE_ADDR 0x50000000
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#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
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#define MX35_SPBA0_SIZE SZ_1M
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#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
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#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
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#define MX35_SSI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x14000)
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#define MX35_ATA_DMA_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x20000)
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#define MX35_MSHC1_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x24000)
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#define MX35_FEC_BASE_ADDR 0x50038000
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#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
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#define MX35_AIPS2_BASE_ADDR 0x53f00000
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#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
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#define MX35_AIPS2_SIZE SZ_1M
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#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
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#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
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#define MX35_EPIT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x94000)
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#define MX35_EPIT2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x98000)
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#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
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#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
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#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
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#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
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#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
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#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
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#define MX35_GPIO2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd0000)
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#define MX35_SDMA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd4000)
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#define MX35_RTC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xd8000)
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#define MX35_WDOG_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xdc000)
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#define MX35_PWM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe0000)
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#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
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#define MX35_OTG_BASE_ADDR 0x53ff4000
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#define MX35_ROMP_BASE_ADDR 0x60000000
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#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
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#define MX35_ROMP_SIZE SZ_1M
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#define MX35_AVIC_BASE_ADDR 0x68000000
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#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
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#define MX35_AVIC_SIZE SZ_1M
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/*
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* Memory regions and CS
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*/
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#define MX35_IPU_MEM_BASE_ADDR 0x70000000
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#define MX35_CSD0_BASE_ADDR 0x80000000
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#define MX35_CSD1_BASE_ADDR 0x90000000
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#define MX35_CS0_BASE_ADDR 0xa0000000
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#define MX35_CS1_BASE_ADDR 0xa8000000
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#define MX35_CS2_BASE_ADDR 0xb0000000
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#define MX35_CS3_BASE_ADDR 0xb2000000
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#define MX35_CS4_BASE_ADDR 0xb4000000
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#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000
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#define MX35_CS4_SIZE SZ_32M
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#define MX35_CS5_BASE_ADDR 0xb6000000
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#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000
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#define MX35_CS5_SIZE SZ_32M
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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#define MX35_X_MEMC_BASE_ADDR 0xb8000000
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#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
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#define MX35_X_MEMC_SIZE SZ_64K
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#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
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#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
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#define MX35_M3IF_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x3000)
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#define MX35_EMI_CTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x4000)
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#define MX35_PCMCIA_CTL_BASE_ADDR MX35_EMI_CTL_BASE_ADDR
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#define MX35_NFC_BASE_ADDR 0xbb000000
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#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
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#define MX35_IO_ADDRESS(x) ( \
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IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \
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IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
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IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
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IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
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IMX_IO_ADDRESS(x, MX35_SPBA0))
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/*
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* Interrupt numbers
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*/
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#define MX35_INT_OWIRE 2
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#define MX35_INT_I2C3 3
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#define MX35_INT_I2C2 4
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#define MX35_INT_RTIC 6
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#define MX35_INT_MMC_SDHC1 7
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#define MX35_INT_MMC_SDHC2 8
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#define MX35_INT_MMC_SDHC3 9
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#define MX35_INT_I2C 10
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#define MX35_INT_SSI1 11
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#define MX35_INT_SSI2 12
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#define MX35_INT_CSPI2 13
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#define MX35_INT_CSPI1 14
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#define MX35_INT_ATA 15
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#define MX35_INT_GPU2D 16
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#define MX35_INT_ASRC 17
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#define MX35_INT_UART3 18
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#define MX35_INT_IIM 19
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#define MX35_INT_RNGA 22
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#define MX35_INT_EVTMON 23
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#define MX35_INT_KPP 24
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#define MX35_INT_RTC 25
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#define MX35_INT_PWM 26
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#define MX35_INT_EPIT2 27
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#define MX35_INT_EPIT1 28
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#define MX35_INT_GPT 29
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#define MX35_INT_POWER_FAIL 30
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#define MX35_INT_UART2 32
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#define MX35_INT_NANDFC 33
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#define MX35_INT_SDMA 34
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#define MX35_INT_USBHS 35
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#define MX35_INT_USBOTG 37
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#define MX35_INT_MSHC1 39
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#define MX35_INT_ESAI 40
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#define MX35_INT_IPU_ERR 41
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#define MX35_INT_IPU_SYN 42
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#define MX35_INT_CAN1 43
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#define MX35_INT_CAN2 44
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#define MX35_INT_UART1 45
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#define MX35_INT_MLB 46
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#define MX35_INT_SPDIF 47
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#define MX35_INT_ECT 48
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#define MX35_INT_SCC_SCM 49
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#define MX35_INT_SCC_SMN 50
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#define MX35_INT_GPIO2 51
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#define MX35_INT_GPIO1 52
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#define MX35_INT_WDOG 55
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#define MX35_INT_GPIO3 56
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#define MX35_INT_FEC 57
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#define MX35_INT_EXT_POWER 58
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#define MX35_INT_EXT_TEMPER 59
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#define MX35_INT_EXT_SENSOR60 60
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#define MX35_INT_EXT_SENSOR61 61
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#define MX35_INT_EXT_WDOG 62
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#define MX35_INT_EXT_TV 63
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#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
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/* silicon revisions specific to i.MX31 */
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#define MX35_CHIP_REV_1_0 0x10
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#define MX35_CHIP_REV_1_1 0x11
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#define MX35_CHIP_REV_1_2 0x12
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#define MX35_CHIP_REV_1_3 0x13
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#define MX35_CHIP_REV_2_0 0x20
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#define MX35_CHIP_REV_2_1 0x21
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#define MX35_CHIP_REV_2_2 0x22
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#define MX35_CHIP_REV_2_3 0x23
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#define MX35_CHIP_REV_3_0 0x30
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#define MX35_CHIP_REV_3_1 0x31
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#define MX35_CHIP_REV_3_2 0x32
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#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
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#define MX35_SYSTEM_REV_NUM 3
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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/* these should go away */
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#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
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#define MXC_INT_OWIRE MX35_INT_OWIRE
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#define MXC_INT_MMC_SDHC2 MX35_INT_MMC_SDHC2
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#define MXC_INT_MMC_SDHC3 MX35_INT_MMC_SDHC3
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#define MXC_INT_GPU2D MX35_INT_GPU2D
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#define MXC_INT_ASRC MX35_INT_ASRC
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#define MXC_INT_USBHS MX35_INT_USBHS
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#define MXC_INT_USBOTG MX35_INT_USBOTG
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#define MXC_INT_ESAI MX35_INT_ESAI
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#define MXC_INT_CAN1 MX35_INT_CAN1
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#define MXC_INT_CAN2 MX35_INT_CAN2
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#define MXC_INT_MLB MX35_INT_MLB
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#define MXC_INT_SPDIF MX35_INT_SPDIF
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#define MXC_INT_FEC MX35_INT_FEC
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#endif
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#endif /* ifndef __MACH_MX35_H__ */
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