7ba0902028
add csp timer block header and source files Signed-off-by: Leo Chen <leochen@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
82 lines
3.3 KiB
C
82 lines
3.3 KiB
C
/*****************************************************************************
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* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/****************************************************************************/
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/**
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* @file tmrHw_reg.h
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*
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* @brief Definitions for low level Timer registers
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*
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*/
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/****************************************************************************/
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#ifndef _TMRHW_REG_H
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#define _TMRHW_REG_H
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#include <mach/csp/mm_io.h>
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#include <mach/csp/hw_cfg.h>
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/* Base address */
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#define tmrHw_MODULE_BASE_ADDR MM_IO_BASE_TMR
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/*
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This platform has four different timers running at different clock speed
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Timer one (Timer ID 0) runs at 25 MHz
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Timer two (Timer ID 1) runs at 25 MHz
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Timer three (Timer ID 2) runs at 150 MHz
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Timer four (Timer ID 3) runs at 150 MHz
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*/
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#define tmrHw_LOW_FREQUENCY_MHZ 25 /* Always 25MHz from XTAL */
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#define tmrHw_LOW_FREQUENCY_HZ 25000000
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#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
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#define tmrHw_HIGH_FREQUENCY_MHZ 150 /* Always 150MHz for FPGA */
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#define tmrHw_HIGH_FREQUENCY_HZ 150000000
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#else
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#define tmrHw_HIGH_FREQUENCY_HZ HW_CFG_BUS_CLK_HZ
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#define tmrHw_HIGH_FREQUENCY_MHZ (HW_CFG_BUS_CLK_HZ / 1000000)
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#endif
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#define tmrHw_LOW_RESOLUTION_CLOCK tmrHw_LOW_FREQUENCY_HZ
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#define tmrHw_HIGH_RESOLUTION_CLOCK tmrHw_HIGH_FREQUENCY_HZ
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#define tmrHw_MAX_COUNT (0xFFFFFFFF) /* maximum number of count a timer can count */
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#define tmrHw_TIMER_NUM_COUNT (4) /* Number of timer module supported */
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typedef struct {
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uint32_t LoadValue; /* Load value for timer */
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uint32_t CurrentValue; /* Current value for timer */
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uint32_t Control; /* Control register */
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uint32_t InterruptClear; /* Interrupt clear register */
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uint32_t RawInterruptStatus; /* Raw interrupt status */
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uint32_t InterruptStatus; /* Masked interrupt status */
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uint32_t BackgroundLoad; /* Background load value */
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uint32_t padding; /* Padding register */
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} tmrHw_REG_t;
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/* Control bot masks */
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#define tmrHw_CONTROL_TIMER_ENABLE 0x00000080
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#define tmrHw_CONTROL_PERIODIC 0x00000040
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#define tmrHw_CONTROL_INTERRUPT_ENABLE 0x00000020
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#define tmrHw_CONTROL_PRESCALE_MASK 0x0000000C
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#define tmrHw_CONTROL_PRESCALE_1 0x00000000
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#define tmrHw_CONTROL_PRESCALE_16 0x00000004
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#define tmrHw_CONTROL_PRESCALE_256 0x00000008
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#define tmrHw_CONTROL_32BIT 0x00000002
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#define tmrHw_CONTROL_ONESHOT 0x00000001
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#define tmrHw_CONTROL_FREE_RUNNING 0x00000000
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#define tmrHw_CONTROL_MODE_MASK (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
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#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
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#endif /* _TMRHW_REG_H */
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