c7bb4fc16e
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
97 lines
2.4 KiB
C
97 lines
2.4 KiB
C
/*
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* MOXA ART SoCs clock driver.
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*
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* Copyright (C) 2013 Jonas Jensen
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*
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* Jonas Jensen <jonas.jensen@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/clkdev.h>
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void __init moxart_of_pll_clk_init(struct device_node *node)
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{
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static void __iomem *base;
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struct clk *clk, *ref_clk;
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unsigned int mul;
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const char *name = node->name;
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const char *parent_name;
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of_property_read_string(node, "clock-output-names", &name);
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parent_name = of_clk_get_parent_name(node, 0);
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("%s: of_iomap failed\n", node->full_name);
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return;
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}
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mul = readl(base + 0x30) >> 3 & 0x3f;
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iounmap(base);
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ref_clk = of_clk_get(node, 0);
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if (IS_ERR(ref_clk)) {
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pr_err("%s: of_clk_get failed\n", node->full_name);
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return;
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}
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clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock\n", node->full_name);
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return;
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}
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clk_register_clkdev(clk, NULL, name);
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
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moxart_of_pll_clk_init);
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void __init moxart_of_apb_clk_init(struct device_node *node)
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{
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static void __iomem *base;
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struct clk *clk, *pll_clk;
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unsigned int div, val;
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unsigned int div_idx[] = { 2, 3, 4, 6, 8};
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const char *name = node->name;
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const char *parent_name;
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of_property_read_string(node, "clock-output-names", &name);
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parent_name = of_clk_get_parent_name(node, 0);
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("%s: of_iomap failed\n", node->full_name);
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return;
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}
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val = readl(base + 0xc) >> 4 & 0x7;
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iounmap(base);
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if (val > 4)
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val = 0;
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div = div_idx[val] * 2;
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pll_clk = of_clk_get(node, 0);
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if (IS_ERR(pll_clk)) {
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pr_err("%s: of_clk_get failed\n", node->full_name);
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return;
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}
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clk = clk_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock\n", node->full_name);
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return;
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}
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clk_register_clkdev(clk, NULL, name);
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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}
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CLK_OF_DECLARE(moxart_apb_clock, "moxa,moxart-apb-clock",
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moxart_of_apb_clk_init);
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