dad0d04fa7
This patch adds the Redpine Signals' 91x wireless driver. Signed-off-by: Fariya Fatima <fariyaf@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
126 lines
4 KiB
C
126 lines
4 KiB
C
/**
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* Copyright (c) 2014 Redpine Signals Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __RSI_BOOTPARAMS_HEADER_H__
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#define __RSI_BOOTPARAMS_HEADER_H__
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#define CRYSTAL_GOOD_TIME BIT(0)
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#define BOOTUP_MODE_INFO BIT(1)
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#define WIFI_TAPLL_CONFIGS BIT(5)
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#define WIFI_PLL960_CONFIGS BIT(6)
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#define WIFI_AFEPLL_CONFIGS BIT(7)
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#define WIFI_SWITCH_CLK_CONFIGS BIT(8)
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#define TA_PLL_M_VAL_20 8
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#define TA_PLL_N_VAL_20 1
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#define TA_PLL_P_VAL_20 4
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#define PLL960_M_VAL_20 0x14
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#define PLL960_N_VAL_20 0
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#define PLL960_P_VAL_20 5
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#define UMAC_CLK_40MHZ 40
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#define TA_PLL_M_VAL_40 46
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#define TA_PLL_N_VAL_40 3
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#define TA_PLL_P_VAL_40 3
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#define PLL960_M_VAL_40 0x14
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#define PLL960_N_VAL_40 0
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#define PLL960_P_VAL_40 5
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#define UMAC_CLK_20BW \
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(((TA_PLL_M_VAL_20 + 1) * 40) / \
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((TA_PLL_N_VAL_20 + 1) * (TA_PLL_P_VAL_20 + 1)))
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#define VALID_20 \
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(WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS)
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#define UMAC_CLK_40BW \
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(((TA_PLL_M_VAL_40 + 1) * 40) / \
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((TA_PLL_N_VAL_40 + 1) * (TA_PLL_P_VAL_40 + 1)))
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#define VALID_40 \
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(WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS | \
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WIFI_TAPLL_CONFIGS | CRYSTAL_GOOD_TIME | BOOTUP_MODE_INFO)
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/* structure to store configs related to TAPLL programming */
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struct tapll_info {
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__le16 pll_reg_1;
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__le16 pll_reg_2;
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} __packed;
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/* structure to store configs related to PLL960 programming */
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struct pll960_info {
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__le16 pll_reg_1;
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__le16 pll_reg_2;
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__le16 pll_reg_3;
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} __packed;
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/* structure to store configs related to AFEPLL programming */
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struct afepll_info {
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__le16 pll_reg;
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} __packed;
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/* structure to store configs related to pll configs */
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struct pll_config {
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struct tapll_info tapll_info_g;
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struct pll960_info pll960_info_g;
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struct afepll_info afepll_info_g;
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} __packed;
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/* structure to store configs related to UMAC clk programming */
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struct switch_clk {
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__le16 switch_clk_info;
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/* If switch_bbp_lmac_clk_reg is set then this value will be programmed
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* into reg
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*/
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__le16 bbp_lmac_clk_reg_val;
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/* if switch_umac_clk is set then this value will be programmed */
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__le16 umac_clock_reg_config;
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/* if switch_qspi_clk is set then this value will be programmed */
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__le16 qspi_uart_clock_reg_config;
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} __packed;
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struct device_clk_info {
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struct pll_config pll_config_g;
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struct switch_clk switch_clk_g;
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} __packed;
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struct bootup_params {
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__le16 magic_number;
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__le16 crystal_good_time;
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__le32 valid;
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__le32 reserved_for_valids;
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__le16 bootup_mode_info;
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/* configuration used for digital loop back */
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__le16 digital_loop_back_params;
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__le16 rtls_timestamp_en;
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__le16 host_spi_intr_cfg;
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struct device_clk_info device_clk_info[3];
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/* ulp buckboost wait time */
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__le32 buckboost_wakeup_cnt;
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/* pmu wakeup wait time & WDT EN info */
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__le16 pmu_wakeup_wait;
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u8 shutdown_wait_time;
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/* Sleep clock source selection */
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u8 pmu_slp_clkout_sel;
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/* WDT programming values */
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__le32 wdt_prog_value;
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/* WDT soc reset delay */
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__le32 wdt_soc_rst_delay;
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/* dcdc modes configs */
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__le32 dcdc_operation_mode;
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__le32 soc_reset_wait_cnt;
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} __packed;
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#endif
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