2a5cfec947
Add defines to make more human readable numbers for the lpass clock controller found on IPQ806x SoCs. Also remove the PLL4 define in gcc to avoid #define conflicts because that clock doesn't exist in gcc, instead it lives in lcc. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Split off into separate patch] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Tested-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
292 lines
8.3 KiB
C
292 lines
8.3 KiB
C
/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_GCC_IPQ806X_H
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#define _DT_BINDINGS_CLK_GCC_IPQ806X_H
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#define AFAB_CLK_SRC 0
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#define QDSS_STM_CLK 1
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#define SCSS_A_CLK 2
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#define SCSS_H_CLK 3
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#define AFAB_CORE_CLK 4
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#define SCSS_XO_SRC_CLK 5
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#define AFAB_EBI1_CH0_A_CLK 6
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#define AFAB_EBI1_CH1_A_CLK 7
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#define AFAB_AXI_S0_FCLK 8
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#define AFAB_AXI_S1_FCLK 9
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#define AFAB_AXI_S2_FCLK 10
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#define AFAB_AXI_S3_FCLK 11
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#define AFAB_AXI_S4_FCLK 12
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#define SFAB_CORE_CLK 13
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#define SFAB_AXI_S0_FCLK 14
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#define SFAB_AXI_S1_FCLK 15
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#define SFAB_AXI_S2_FCLK 16
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#define SFAB_AXI_S3_FCLK 17
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#define SFAB_AXI_S4_FCLK 18
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#define SFAB_AXI_S5_FCLK 19
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#define SFAB_AHB_S0_FCLK 20
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#define SFAB_AHB_S1_FCLK 21
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#define SFAB_AHB_S2_FCLK 22
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#define SFAB_AHB_S3_FCLK 23
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#define SFAB_AHB_S4_FCLK 24
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#define SFAB_AHB_S5_FCLK 25
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#define SFAB_AHB_S6_FCLK 26
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#define SFAB_AHB_S7_FCLK 27
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#define QDSS_AT_CLK_SRC 28
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#define QDSS_AT_CLK 29
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#define QDSS_TRACECLKIN_CLK_SRC 30
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#define QDSS_TRACECLKIN_CLK 31
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#define QDSS_TSCTR_CLK_SRC 32
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#define QDSS_TSCTR_CLK 33
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#define SFAB_ADM0_M0_A_CLK 34
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#define SFAB_ADM0_M1_A_CLK 35
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#define SFAB_ADM0_M2_H_CLK 36
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#define ADM0_CLK 37
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#define ADM0_PBUS_CLK 38
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#define IMEM0_A_CLK 39
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#define QDSS_H_CLK 40
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#define PCIE_A_CLK 41
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#define PCIE_AUX_CLK 42
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#define PCIE_H_CLK 43
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#define PCIE_PHY_CLK 44
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#define SFAB_CLK_SRC 45
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#define SFAB_LPASS_Q6_A_CLK 46
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#define SFAB_AFAB_M_A_CLK 47
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#define AFAB_SFAB_M0_A_CLK 48
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#define AFAB_SFAB_M1_A_CLK 49
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#define SFAB_SATA_S_H_CLK 50
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#define DFAB_CLK_SRC 51
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#define DFAB_CLK 52
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#define SFAB_DFAB_M_A_CLK 53
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#define DFAB_SFAB_M_A_CLK 54
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#define DFAB_SWAY0_H_CLK 55
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#define DFAB_SWAY1_H_CLK 56
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#define DFAB_ARB0_H_CLK 57
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#define DFAB_ARB1_H_CLK 58
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#define PPSS_H_CLK 59
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#define PPSS_PROC_CLK 60
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#define PPSS_TIMER0_CLK 61
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#define PPSS_TIMER1_CLK 62
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#define PMEM_A_CLK 63
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#define DMA_BAM_H_CLK 64
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#define SIC_H_CLK 65
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#define SPS_TIC_H_CLK 66
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#define CFPB_2X_CLK_SRC 67
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#define CFPB_CLK 68
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#define CFPB0_H_CLK 69
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#define CFPB1_H_CLK 70
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#define CFPB2_H_CLK 71
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#define SFAB_CFPB_M_H_CLK 72
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#define CFPB_MASTER_H_CLK 73
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#define SFAB_CFPB_S_H_CLK 74
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#define CFPB_SPLITTER_H_CLK 75
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#define TSIF_H_CLK 76
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#define TSIF_INACTIVITY_TIMERS_CLK 77
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#define TSIF_REF_SRC 78
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#define TSIF_REF_CLK 79
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#define CE1_H_CLK 80
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#define CE1_CORE_CLK 81
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#define CE1_SLEEP_CLK 82
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#define CE2_H_CLK 83
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#define CE2_CORE_CLK 84
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#define SFPB_H_CLK_SRC 85
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#define SFPB_H_CLK 86
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#define SFAB_SFPB_M_H_CLK 87
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#define SFAB_SFPB_S_H_CLK 88
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#define RPM_PROC_CLK 89
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#define RPM_BUS_H_CLK 90
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#define RPM_SLEEP_CLK 91
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#define RPM_TIMER_CLK 92
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#define RPM_MSG_RAM_H_CLK 93
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#define PMIC_ARB0_H_CLK 94
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#define PMIC_ARB1_H_CLK 95
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#define PMIC_SSBI2_SRC 96
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#define PMIC_SSBI2_CLK 97
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#define SDC1_H_CLK 98
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#define SDC2_H_CLK 99
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#define SDC3_H_CLK 100
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#define SDC4_H_CLK 101
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#define SDC1_SRC 102
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#define SDC1_CLK 103
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#define SDC2_SRC 104
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#define SDC2_CLK 105
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#define SDC3_SRC 106
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#define SDC3_CLK 107
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#define SDC4_SRC 108
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#define SDC4_CLK 109
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#define USB_HS1_H_CLK 110
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#define USB_HS1_XCVR_SRC 111
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#define USB_HS1_XCVR_CLK 112
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#define USB_HSIC_H_CLK 113
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#define USB_HSIC_XCVR_SRC 114
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#define USB_HSIC_XCVR_CLK 115
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#define USB_HSIC_SYSTEM_CLK_SRC 116
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#define USB_HSIC_SYSTEM_CLK 117
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#define CFPB0_C0_H_CLK 118
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#define CFPB0_D0_H_CLK 119
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#define CFPB0_C1_H_CLK 120
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#define CFPB0_D1_H_CLK 121
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#define USB_FS1_H_CLK 122
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#define USB_FS1_XCVR_SRC 123
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#define USB_FS1_XCVR_CLK 124
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#define USB_FS1_SYSTEM_CLK 125
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#define GSBI_COMMON_SIM_SRC 126
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#define GSBI1_H_CLK 127
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#define GSBI2_H_CLK 128
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#define GSBI3_H_CLK 129
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#define GSBI4_H_CLK 130
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#define GSBI5_H_CLK 131
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#define GSBI6_H_CLK 132
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#define GSBI7_H_CLK 133
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#define GSBI1_QUP_SRC 134
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#define GSBI1_QUP_CLK 135
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#define GSBI2_QUP_SRC 136
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#define GSBI2_QUP_CLK 137
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#define GSBI3_QUP_SRC 138
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#define GSBI3_QUP_CLK 139
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#define GSBI4_QUP_SRC 140
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#define GSBI4_QUP_CLK 141
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#define GSBI5_QUP_SRC 142
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#define GSBI5_QUP_CLK 143
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#define GSBI6_QUP_SRC 144
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#define GSBI6_QUP_CLK 145
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#define GSBI7_QUP_SRC 146
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#define GSBI7_QUP_CLK 147
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#define GSBI1_UART_SRC 148
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#define GSBI1_UART_CLK 149
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#define GSBI2_UART_SRC 150
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#define GSBI2_UART_CLK 151
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#define GSBI3_UART_SRC 152
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#define GSBI3_UART_CLK 153
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#define GSBI4_UART_SRC 154
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#define GSBI4_UART_CLK 155
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#define GSBI5_UART_SRC 156
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#define GSBI5_UART_CLK 157
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#define GSBI6_UART_SRC 158
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#define GSBI6_UART_CLK 159
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#define GSBI7_UART_SRC 160
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#define GSBI7_UART_CLK 161
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#define GSBI1_SIM_CLK 162
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#define GSBI2_SIM_CLK 163
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#define GSBI3_SIM_CLK 164
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#define GSBI4_SIM_CLK 165
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#define GSBI5_SIM_CLK 166
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#define GSBI6_SIM_CLK 167
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#define GSBI7_SIM_CLK 168
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#define USB_HSIC_HSIC_CLK_SRC 169
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#define USB_HSIC_HSIC_CLK 170
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#define USB_HSIC_HSIO_CAL_CLK 171
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#define SPDM_CFG_H_CLK 172
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#define SPDM_MSTR_H_CLK 173
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#define SPDM_FF_CLK_SRC 174
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#define SPDM_FF_CLK 175
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#define SEC_CTRL_CLK 176
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#define SEC_CTRL_ACC_CLK_SRC 177
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#define SEC_CTRL_ACC_CLK 178
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#define TLMM_H_CLK 179
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#define TLMM_CLK 180
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#define SATA_H_CLK 181
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#define SATA_CLK_SRC 182
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#define SATA_RXOOB_CLK 183
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#define SATA_PMALIVE_CLK 184
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#define SATA_PHY_REF_CLK 185
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#define SATA_A_CLK 186
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#define SATA_PHY_CFG_CLK 187
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#define TSSC_CLK_SRC 188
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#define TSSC_CLK 189
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#define PDM_SRC 190
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#define PDM_CLK 191
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#define GP0_SRC 192
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#define GP0_CLK 193
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#define GP1_SRC 194
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#define GP1_CLK 195
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#define GP2_SRC 196
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#define GP2_CLK 197
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#define MPM_CLK 198
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#define EBI1_CLK_SRC 199
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#define EBI1_CH0_CLK 200
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#define EBI1_CH1_CLK 201
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#define EBI1_2X_CLK 202
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#define EBI1_CH0_DQ_CLK 203
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#define EBI1_CH1_DQ_CLK 204
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#define EBI1_CH0_CA_CLK 205
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#define EBI1_CH1_CA_CLK 206
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#define EBI1_XO_CLK 207
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#define SFAB_SMPSS_S_H_CLK 208
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#define PRNG_SRC 209
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#define PRNG_CLK 210
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#define PXO_SRC 211
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#define SPDM_CY_PORT0_CLK 212
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#define SPDM_CY_PORT1_CLK 213
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#define SPDM_CY_PORT2_CLK 214
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#define SPDM_CY_PORT3_CLK 215
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#define SPDM_CY_PORT4_CLK 216
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#define SPDM_CY_PORT5_CLK 217
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#define SPDM_CY_PORT6_CLK 218
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#define SPDM_CY_PORT7_CLK 219
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#define PLL0 220
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#define PLL0_VOTE 221
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#define PLL3 222
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#define PLL3_VOTE 223
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#define PLL4_VOTE 225
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#define PLL8 226
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#define PLL8_VOTE 227
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#define PLL9 228
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#define PLL10 229
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#define PLL11 230
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#define PLL12 231
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#define PLL14 232
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#define PLL14_VOTE 233
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#define PLL18 234
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#define CE5_SRC 235
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#define CE5_H_CLK 236
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#define CE5_CORE_CLK 237
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#define CE3_SLEEP_CLK 238
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#define SFAB_AHB_S8_FCLK 239
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#define SPDM_CY_PORT8_CLK 246
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#define PCIE_ALT_REF_SRC 247
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#define PCIE_ALT_REF_CLK 248
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#define PCIE_1_A_CLK 249
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#define PCIE_1_AUX_CLK 250
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#define PCIE_1_H_CLK 251
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#define PCIE_1_PHY_CLK 252
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#define PCIE_1_ALT_REF_SRC 253
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#define PCIE_1_ALT_REF_CLK 254
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#define PCIE_2_A_CLK 255
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#define PCIE_2_AUX_CLK 256
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#define PCIE_2_H_CLK 257
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#define PCIE_2_PHY_CLK 258
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#define PCIE_2_ALT_REF_SRC 259
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#define PCIE_2_ALT_REF_CLK 260
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#define EBI2_CLK 261
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#define USB30_SLEEP_CLK 262
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#define USB30_UTMI_SRC 263
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#define USB30_0_UTMI_CLK 264
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#define USB30_1_UTMI_CLK 265
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#define USB30_MASTER_SRC 266
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#define USB30_0_MASTER_CLK 267
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#define USB30_1_MASTER_CLK 268
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#define GMAC_CORE1_CLK_SRC 269
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#define GMAC_CORE2_CLK_SRC 270
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#define GMAC_CORE3_CLK_SRC 271
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#define GMAC_CORE4_CLK_SRC 272
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#define GMAC_CORE1_CLK 273
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#define GMAC_CORE2_CLK 274
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#define GMAC_CORE3_CLK 275
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#define GMAC_CORE4_CLK 276
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#define UBI32_CORE1_CLK_SRC 277
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#define UBI32_CORE2_CLK_SRC 278
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#define UBI32_CORE1_CLK 279
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#define UBI32_CORE2_CLK 280
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#endif
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