82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
#ifndef __ASM_SH_HITACHI_SE7343_H
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#define __ASM_SH_HITACHI_SE7343_H
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/*
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* include/asm-sh/se/se7343.h
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*
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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*
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* SH-Mobile SolutionEngine 7343 support
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*/
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/* Box specific addresses. */
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/* Area 0 */
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#define PA_ROM 0x00000000 /* EPROM */
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#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
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#define PA_FROM 0x00400000 /* Flash ROM */
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#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
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#define PA_SRAM 0x00800000 /* SRAM */
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#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
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/* Area 1 */
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#define PA_EXT1 0x04000000
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#define PA_EXT1_SIZE 0x04000000
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/* Area 2 */
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#define PA_EXT2 0x08000000
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#define PA_EXT2_SIZE 0x04000000
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/* Area 3 */
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#define PA_SDRAM 0x0c000000
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#define PA_SDRAM_SIZE 0x04000000
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/* Area 4 */
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#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */
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#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */
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#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */
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#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */
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#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */
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#define MRSHPC_OPTION (PA_MRSHPC + 6)
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#define MRSHPC_CSR (PA_MRSHPC + 8)
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#define MRSHPC_ISR (PA_MRSHPC + 10)
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#define MRSHPC_ICR (PA_MRSHPC + 12)
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#define MRSHPC_CPWCR (PA_MRSHPC + 14)
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#define MRSHPC_MW0CR1 (PA_MRSHPC + 16)
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#define MRSHPC_MW1CR1 (PA_MRSHPC + 18)
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#define MRSHPC_IOWCR1 (PA_MRSHPC + 20)
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#define MRSHPC_MW0CR2 (PA_MRSHPC + 22)
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#define MRSHPC_MW1CR2 (PA_MRSHPC + 24)
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#define MRSHPC_IOWCR2 (PA_MRSHPC + 26)
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#define MRSHPC_CDCR (PA_MRSHPC + 28)
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#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
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#define PA_LED 0xb0C00000 /* LED */
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#define LED_SHIFT 0
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#define PA_DIPSW 0xb0900000 /* Dip switch 31 */
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#define PA_CPLD_MODESET 0xb1400004 /* CPLD Mode set register */
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#define PA_CPLD_ST 0xb1400008 /* CPLD Interrupt status register */
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#define PA_CPLD_IMSK 0xb140000a /* CPLD Interrupt mask register */
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/* Area 5 */
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#define PA_EXT5 0x14000000
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#define PA_EXT5_SIZE 0x04000000
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/* Area 6 */
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#define PA_LCD1 0xb8000000
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#define PA_LCD2 0xb8800000
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#define __IO_PREFIX sh7343se
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#include <asm/io_generic.h>
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/* External Multiplexed interrupts */
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#define PC_IRQ0 OFFCHIP_IRQ_BASE
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#define PC_IRQ1 (PC_IRQ0 + 1)
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#define PC_IRQ2 (PC_IRQ1 + 1)
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#define PC_IRQ3 (PC_IRQ2 + 1)
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#define EXT_IRQ0 (PC_IRQ3 + 1)
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#define EXT_IRQ1 (EXT_IRQ0 + 1)
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#define EXT_IRQ2 (EXT_IRQ1 + 1)
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#define EXT_IRQ3 (EXT_IRQ2 + 1)
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#define USB_IRQ0 (EXT_IRQ3 + 1)
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#define USB_IRQ1 (USB_IRQ0 + 1)
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#define UART_IRQ0 (USB_IRQ1 + 1)
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#define UART_IRQ1 (UART_IRQ0 + 1)
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#endif /* __ASM_SH_HITACHI_SE7343_H */
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