c5c8635a04
Add platform driver for the Qualcomm Technologies low-power audio subsystem (LPASS) ports. Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org> Acked-by: Banajit Goswami <bgoswami@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
526 lines
14 KiB
C
526 lines
14 KiB
C
/*
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* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* lpass-platform.c -- ALSA SoC platform driver for QTi LPASS
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*/
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#include <linux/compiler.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <sound/memalloc.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#include "lpass-lpaif-ipq806x.h"
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#include "lpass.h"
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#define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024)
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#define LPASS_PLATFORM_PERIODS 2
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static struct snd_pcm_hardware lpass_platform_pcm_hardware = {
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.info = SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_PAUSE |
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SNDRV_PCM_INFO_RESUME,
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.formats = SNDRV_PCM_FMTBIT_S16 |
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SNDRV_PCM_FMTBIT_S24 |
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SNDRV_PCM_FMTBIT_S32,
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.rates = SNDRV_PCM_RATE_8000_192000,
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.rate_min = 8000,
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.rate_max = 192000,
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.channels_min = 1,
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.channels_max = 8,
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.buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE,
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.period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE /
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LPASS_PLATFORM_PERIODS,
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.period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE /
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LPASS_PLATFORM_PERIODS,
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.periods_min = LPASS_PLATFORM_PERIODS,
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.periods_max = LPASS_PLATFORM_PERIODS,
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.fifo_size = 0,
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};
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static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
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int ret;
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snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware);
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runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max;
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ret = snd_pcm_hw_constraint_integer(runtime,
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SNDRV_PCM_HW_PARAM_PERIODS);
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if (ret < 0) {
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dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n",
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__func__, ret);
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return -EINVAL;
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}
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snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
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return 0;
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}
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static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
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struct lpass_data *drvdata =
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snd_soc_platform_get_drvdata(soc_runtime->platform);
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snd_pcm_format_t format = params_format(params);
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unsigned int channels = params_channels(params);
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unsigned int regval;
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int bitwidth;
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int ret;
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bitwidth = snd_pcm_format_width(format);
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if (bitwidth < 0) {
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dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n",
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__func__, bitwidth);
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return bitwidth;
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}
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regval = LPAIF_RDMACTL_BURSTEN_INCR4 |
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LPAIF_RDMACTL_AUDINTF_MI2S |
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LPAIF_RDMACTL_FIFOWM_8;
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switch (bitwidth) {
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case 16:
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switch (channels) {
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case 1:
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case 2:
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regval |= LPAIF_RDMACTL_WPSCNT_ONE;
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break;
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case 4:
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regval |= LPAIF_RDMACTL_WPSCNT_TWO;
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break;
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case 6:
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regval |= LPAIF_RDMACTL_WPSCNT_THREE;
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break;
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case 8:
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regval |= LPAIF_RDMACTL_WPSCNT_FOUR;
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break;
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default:
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dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
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__func__, bitwidth, channels);
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return -EINVAL;
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}
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break;
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case 24:
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case 32:
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switch (channels) {
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case 1:
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regval |= LPAIF_RDMACTL_WPSCNT_ONE;
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break;
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case 2:
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regval |= LPAIF_RDMACTL_WPSCNT_TWO;
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break;
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case 4:
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regval |= LPAIF_RDMACTL_WPSCNT_FOUR;
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break;
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case 6:
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regval |= LPAIF_RDMACTL_WPSCNT_SIX;
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break;
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case 8:
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regval |= LPAIF_RDMACTL_WPSCNT_EIGHT;
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break;
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default:
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dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
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__func__, bitwidth, channels);
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return -EINVAL;
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}
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break;
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default:
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dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n",
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__func__, bitwidth, channels);
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return -EINVAL;
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}
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), regval);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
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__func__, ret);
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return ret;
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}
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return 0;
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}
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static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
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struct lpass_data *drvdata =
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snd_soc_platform_get_drvdata(soc_runtime->platform);
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int ret;
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), 0);
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if (ret)
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dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
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__func__, ret);
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return ret;
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}
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static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
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struct lpass_data *drvdata =
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snd_soc_platform_get_drvdata(soc_runtime->platform);
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int ret;
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_RDMABASE_REG(LPAIF_RDMA_CHAN_MI2S),
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runtime->dma_addr);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n",
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__func__, ret);
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return ret;
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}
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_RDMABUFF_REG(LPAIF_RDMA_CHAN_MI2S),
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(snd_pcm_lib_buffer_bytes(substream) >> 2) - 1);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n",
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__func__, ret);
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return ret;
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}
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_RDMAPER_REG(LPAIF_RDMA_CHAN_MI2S),
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(snd_pcm_lib_period_bytes(substream) >> 2) - 1);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n",
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__func__, ret);
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return ret;
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}
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ret = regmap_update_bits(drvdata->lpaif_map,
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LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S),
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LPAIF_RDMACTL_ENABLE_MASK, LPAIF_RDMACTL_ENABLE_ON);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
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__func__, ret);
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return ret;
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}
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return 0;
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}
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static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream,
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int cmd)
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{
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struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
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struct lpass_data *drvdata =
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snd_soc_platform_get_drvdata(soc_runtime->platform);
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int ret;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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/* clear status before enabling interrupts */
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST),
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LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S));
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
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__func__, ret);
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return ret;
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}
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ret = regmap_update_bits(drvdata->lpaif_map,
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LPAIF_IRQEN_REG(LPAIF_IRQ_PORT_HOST),
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LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S),
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LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S));
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
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__func__, ret);
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return ret;
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}
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ret = regmap_update_bits(drvdata->lpaif_map,
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LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S),
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LPAIF_RDMACTL_ENABLE_MASK,
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LPAIF_RDMACTL_ENABLE_ON);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
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__func__, ret);
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return ret;
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}
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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ret = regmap_update_bits(drvdata->lpaif_map,
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LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S),
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LPAIF_RDMACTL_ENABLE_MASK,
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LPAIF_RDMACTL_ENABLE_OFF);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
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__func__, ret);
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return ret;
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}
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ret = regmap_update_bits(drvdata->lpaif_map,
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LPAIF_IRQEN_REG(LPAIF_IRQ_PORT_HOST),
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LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S), 0);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
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__func__, ret);
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return ret;
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}
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break;
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}
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return 0;
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}
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static snd_pcm_uframes_t lpass_platform_pcmops_pointer(
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struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
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struct lpass_data *drvdata =
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snd_soc_platform_get_drvdata(soc_runtime->platform);
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unsigned int base_addr, curr_addr;
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int ret;
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ret = regmap_read(drvdata->lpaif_map,
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LPAIF_RDMABASE_REG(LPAIF_RDMA_CHAN_MI2S), &base_addr);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n",
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__func__, ret);
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return ret;
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}
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ret = regmap_read(drvdata->lpaif_map,
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LPAIF_RDMACURR_REG(LPAIF_RDMA_CHAN_MI2S), &curr_addr);
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if (ret) {
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dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n",
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__func__, ret);
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return ret;
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}
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return bytes_to_frames(substream->runtime, curr_addr - base_addr);
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}
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static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream,
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struct vm_area_struct *vma)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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return dma_mmap_coherent(substream->pcm->card->dev, vma,
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runtime->dma_area, runtime->dma_addr,
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runtime->dma_bytes);
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}
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static struct snd_pcm_ops lpass_platform_pcm_ops = {
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.open = lpass_platform_pcmops_open,
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.ioctl = snd_pcm_lib_ioctl,
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.hw_params = lpass_platform_pcmops_hw_params,
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.hw_free = lpass_platform_pcmops_hw_free,
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.prepare = lpass_platform_pcmops_prepare,
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.trigger = lpass_platform_pcmops_trigger,
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.pointer = lpass_platform_pcmops_pointer,
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.mmap = lpass_platform_pcmops_mmap,
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};
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static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data)
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{
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struct snd_pcm_substream *substream = data;
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struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
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struct lpass_data *drvdata =
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snd_soc_platform_get_drvdata(soc_runtime->platform);
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unsigned int interrupts;
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irqreturn_t ret = IRQ_NONE;
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int rv;
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rv = regmap_read(drvdata->lpaif_map,
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LPAIF_IRQSTAT_REG(LPAIF_IRQ_PORT_HOST), &interrupts);
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if (rv) {
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dev_err(soc_runtime->dev, "%s() error reading from irqstat reg: %d\n",
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__func__, rv);
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return IRQ_NONE;
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}
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interrupts &= LPAIF_IRQ_ALL(LPAIF_RDMA_CHAN_MI2S);
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if (interrupts & LPAIF_IRQ_PER(LPAIF_RDMA_CHAN_MI2S)) {
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rv = regmap_write(drvdata->lpaif_map,
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LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST),
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LPAIF_IRQ_PER(LPAIF_RDMA_CHAN_MI2S));
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if (rv) {
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dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
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__func__, rv);
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return IRQ_NONE;
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}
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snd_pcm_period_elapsed(substream);
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ret = IRQ_HANDLED;
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}
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if (interrupts & LPAIF_IRQ_XRUN(LPAIF_RDMA_CHAN_MI2S)) {
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rv = regmap_write(drvdata->lpaif_map,
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LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST),
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LPAIF_IRQ_XRUN(LPAIF_RDMA_CHAN_MI2S));
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if (rv) {
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dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
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__func__, rv);
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return IRQ_NONE;
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}
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dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__);
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snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
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ret = IRQ_HANDLED;
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}
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if (interrupts & LPAIF_IRQ_ERR(LPAIF_RDMA_CHAN_MI2S)) {
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rv = regmap_write(drvdata->lpaif_map,
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LPAIF_IRQCLEAR_REG(LPAIF_IRQ_PORT_HOST),
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LPAIF_IRQ_ERR(LPAIF_RDMA_CHAN_MI2S));
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if (rv) {
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dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n",
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__func__, rv);
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return IRQ_NONE;
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}
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dev_err(soc_runtime->dev, "%s() bus access error\n", __func__);
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snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
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ret = IRQ_HANDLED;
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}
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return ret;
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}
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static int lpass_platform_alloc_buffer(struct snd_pcm_substream *substream,
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struct snd_soc_pcm_runtime *soc_runtime)
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{
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struct snd_dma_buffer *buf = &substream->dma_buffer;
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size_t size = lpass_platform_pcm_hardware.buffer_bytes_max;
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buf->dev.type = SNDRV_DMA_TYPE_DEV;
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buf->dev.dev = soc_runtime->dev;
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buf->private_data = NULL;
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buf->area = dma_alloc_coherent(soc_runtime->dev, size, &buf->addr,
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GFP_KERNEL);
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if (!buf->area) {
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dev_err(soc_runtime->dev, "%s: Could not allocate DMA buffer\n",
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__func__);
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return -ENOMEM;
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}
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buf->bytes = size;
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return 0;
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}
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static void lpass_platform_free_buffer(struct snd_pcm_substream *substream,
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struct snd_soc_pcm_runtime *soc_runtime)
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{
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struct snd_dma_buffer *buf = &substream->dma_buffer;
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if (buf->area) {
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dma_free_coherent(soc_runtime->dev, buf->bytes, buf->area,
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buf->addr);
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}
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buf->area = NULL;
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}
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static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime)
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{
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struct snd_pcm *pcm = soc_runtime->pcm;
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struct snd_pcm_substream *substream =
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pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
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struct lpass_data *drvdata =
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snd_soc_platform_get_drvdata(soc_runtime->platform);
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int ret;
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soc_runtime->dev->coherent_dma_mask = DMA_BIT_MASK(32);
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soc_runtime->dev->dma_mask = &soc_runtime->dev->coherent_dma_mask;
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ret = lpass_platform_alloc_buffer(substream, soc_runtime);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = devm_request_irq(soc_runtime->dev, drvdata->lpaif_irq,
|
|
lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING,
|
|
"lpass-irq-lpaif", substream);
|
|
if (ret) {
|
|
dev_err(soc_runtime->dev, "%s() irq request failed: %d\n",
|
|
__func__, ret);
|
|
goto err_buf;
|
|
}
|
|
|
|
/* ensure audio hardware is disabled */
|
|
ret = regmap_write(drvdata->lpaif_map,
|
|
LPAIF_IRQEN_REG(LPAIF_IRQ_PORT_HOST), 0);
|
|
if (ret) {
|
|
dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
ret = regmap_write(drvdata->lpaif_map,
|
|
LPAIF_RDMACTL_REG(LPAIF_RDMA_CHAN_MI2S), 0);
|
|
if (ret) {
|
|
dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_buf:
|
|
lpass_platform_free_buffer(substream, soc_runtime);
|
|
return ret;
|
|
}
|
|
|
|
static void lpass_platform_pcm_free(struct snd_pcm *pcm)
|
|
{
|
|
struct snd_pcm_substream *substream =
|
|
pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
|
|
struct snd_soc_pcm_runtime *soc_runtime = substream->private_data;
|
|
|
|
lpass_platform_free_buffer(substream, soc_runtime);
|
|
}
|
|
|
|
static struct snd_soc_platform_driver lpass_platform_driver = {
|
|
.pcm_new = lpass_platform_pcm_new,
|
|
.pcm_free = lpass_platform_pcm_free,
|
|
.ops = &lpass_platform_pcm_ops,
|
|
};
|
|
|
|
int asoc_qcom_lpass_platform_register(struct platform_device *pdev)
|
|
{
|
|
struct lpass_data *drvdata = platform_get_drvdata(pdev);
|
|
|
|
drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif");
|
|
if (drvdata->lpaif_irq < 0) {
|
|
dev_err(&pdev->dev, "%s() error getting irq handle: %d\n",
|
|
__func__, drvdata->lpaif_irq);
|
|
return -ENODEV;
|
|
}
|
|
|
|
return devm_snd_soc_register_platform(&pdev->dev,
|
|
&lpass_platform_driver);
|
|
}
|
|
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register);
|
|
|
|
MODULE_DESCRIPTION("QTi LPASS Platform Driver");
|
|
MODULE_LICENSE("GPL v2");
|