9a0bf528b4
Raise the DVB frontends one level up, as the intention is to remove the drivers/media/dvb directory. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
447 lines
11 KiB
C
447 lines
11 KiB
C
/*
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VES1820 - Single Chip Cable Channel Receiver driver module
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Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <asm/div64.h>
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#include "dvb_frontend.h"
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#include "ves1820.h"
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struct ves1820_state {
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struct i2c_adapter* i2c;
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/* configuration settings */
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const struct ves1820_config* config;
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struct dvb_frontend frontend;
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/* private demodulator data */
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u8 reg0;
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u8 pwm;
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};
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static int verbose;
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static u8 ves1820_inittab[] = {
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0x69, 0x6A, 0x93, 0x1A, 0x12, 0x46, 0x26, 0x1A,
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0x43, 0x6A, 0xAA, 0xAA, 0x1E, 0x85, 0x43, 0x20,
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0xE0, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
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0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x40
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};
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static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
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{
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u8 buf[] = { 0x00, reg, data };
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struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
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int ret;
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ret = i2c_transfer(state->i2c, &msg, 1);
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if (ret != 1)
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printk("ves1820: %s(): writereg error (reg == 0x%02x, "
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"val == 0x%02x, ret == %i)\n", __func__, reg, data, ret);
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return (ret != 1) ? -EREMOTEIO : 0;
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}
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static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
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{
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u8 b0[] = { 0x00, reg };
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u8 b1[] = { 0 };
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struct i2c_msg msg[] = {
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{.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
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{.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
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};
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int ret;
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ret = i2c_transfer(state->i2c, msg, 2);
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if (ret != 2)
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printk("ves1820: %s(): readreg error (reg == 0x%02x, "
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"ret == %i)\n", __func__, reg, ret);
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return b1[0];
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}
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static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversion)
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{
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reg0 |= state->reg0 & 0x62;
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if (INVERSION_ON == inversion) {
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if (!state->config->invert) reg0 |= 0x20;
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else reg0 &= ~0x20;
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} else if (INVERSION_OFF == inversion) {
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if (!state->config->invert) reg0 &= ~0x20;
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else reg0 |= 0x20;
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}
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ves1820_writereg(state, 0x00, reg0 & 0xfe);
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ves1820_writereg(state, 0x00, reg0 | 0x01);
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state->reg0 = reg0;
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return 0;
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}
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static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
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{
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s32 BDR;
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s32 BDRI;
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s16 SFIL = 0;
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u16 NDEC = 0;
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u32 ratio;
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u32 fin;
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u32 tmp;
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u64 fptmp;
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u64 fpxin;
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if (symbolrate > state->config->xin / 2)
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symbolrate = state->config->xin / 2;
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if (symbolrate < 500000)
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symbolrate = 500000;
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if (symbolrate < state->config->xin / 16)
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NDEC = 1;
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if (symbolrate < state->config->xin / 32)
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NDEC = 2;
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if (symbolrate < state->config->xin / 64)
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NDEC = 3;
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/* yeuch! */
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fpxin = state->config->xin * 10;
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fptmp = fpxin; do_div(fptmp, 123);
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if (symbolrate < fptmp)
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SFIL = 1;
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fptmp = fpxin; do_div(fptmp, 160);
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if (symbolrate < fptmp)
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SFIL = 0;
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fptmp = fpxin; do_div(fptmp, 246);
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if (symbolrate < fptmp)
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SFIL = 1;
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fptmp = fpxin; do_div(fptmp, 320);
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if (symbolrate < fptmp)
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SFIL = 0;
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fptmp = fpxin; do_div(fptmp, 492);
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if (symbolrate < fptmp)
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SFIL = 1;
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fptmp = fpxin; do_div(fptmp, 640);
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if (symbolrate < fptmp)
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SFIL = 0;
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fptmp = fpxin; do_div(fptmp, 984);
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if (symbolrate < fptmp)
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SFIL = 1;
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fin = state->config->xin >> 4;
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symbolrate <<= NDEC;
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ratio = (symbolrate << 4) / fin;
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tmp = ((symbolrate << 4) % fin) << 8;
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ratio = (ratio << 8) + tmp / fin;
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tmp = (tmp % fin) << 8;
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ratio = (ratio << 8) + DIV_ROUND_CLOSEST(tmp, fin);
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BDR = ratio;
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BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
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if (BDRI > 0xFF)
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BDRI = 0xFF;
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SFIL = (SFIL << 4) | ves1820_inittab[0x0E];
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NDEC = (NDEC << 6) | ves1820_inittab[0x03];
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ves1820_writereg(state, 0x03, NDEC);
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ves1820_writereg(state, 0x0a, BDR & 0xff);
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ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
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ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
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ves1820_writereg(state, 0x0d, BDRI);
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ves1820_writereg(state, 0x0e, SFIL);
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return 0;
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}
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static int ves1820_init(struct dvb_frontend* fe)
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{
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struct ves1820_state* state = fe->demodulator_priv;
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int i;
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ves1820_writereg(state, 0, 0);
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for (i = 0; i < sizeof(ves1820_inittab); i++)
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ves1820_writereg(state, i, ves1820_inittab[i]);
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if (state->config->selagc)
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ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);
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ves1820_writereg(state, 0x34, state->pwm);
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return 0;
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}
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static int ves1820_set_parameters(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct ves1820_state* state = fe->demodulator_priv;
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static const u8 reg0x00[] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
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static const u8 reg0x01[] = { 140, 140, 106, 100, 92 };
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static const u8 reg0x05[] = { 135, 100, 70, 54, 38 };
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static const u8 reg0x08[] = { 162, 116, 67, 52, 35 };
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static const u8 reg0x09[] = { 145, 150, 106, 126, 107 };
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int real_qam = p->modulation - QAM_16;
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if (real_qam < 0 || real_qam > 4)
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return -EINVAL;
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if (fe->ops.tuner_ops.set_params) {
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fe->ops.tuner_ops.set_params(fe);
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if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
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}
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ves1820_set_symbolrate(state, p->symbol_rate);
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ves1820_writereg(state, 0x34, state->pwm);
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ves1820_writereg(state, 0x01, reg0x01[real_qam]);
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ves1820_writereg(state, 0x05, reg0x05[real_qam]);
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ves1820_writereg(state, 0x08, reg0x08[real_qam]);
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ves1820_writereg(state, 0x09, reg0x09[real_qam]);
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ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
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ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));
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return 0;
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}
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static int ves1820_read_status(struct dvb_frontend* fe, fe_status_t* status)
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{
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struct ves1820_state* state = fe->demodulator_priv;
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int sync;
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*status = 0;
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sync = ves1820_readreg(state, 0x11);
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if (sync & 1)
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*status |= FE_HAS_SIGNAL;
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if (sync & 2)
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*status |= FE_HAS_CARRIER;
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if (sync & 2) /* XXX FIXME! */
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*status |= FE_HAS_VITERBI;
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if (sync & 4)
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*status |= FE_HAS_SYNC;
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if (sync & 8)
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*status |= FE_HAS_LOCK;
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return 0;
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}
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static int ves1820_read_ber(struct dvb_frontend* fe, u32* ber)
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{
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struct ves1820_state* state = fe->demodulator_priv;
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u32 _ber = ves1820_readreg(state, 0x14) |
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(ves1820_readreg(state, 0x15) << 8) |
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((ves1820_readreg(state, 0x16) & 0x0f) << 16);
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*ber = 10 * _ber;
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return 0;
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}
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static int ves1820_read_signal_strength(struct dvb_frontend* fe, u16* strength)
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{
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struct ves1820_state* state = fe->demodulator_priv;
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u8 gain = ves1820_readreg(state, 0x17);
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*strength = (gain << 8) | gain;
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return 0;
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}
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static int ves1820_read_snr(struct dvb_frontend* fe, u16* snr)
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{
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struct ves1820_state* state = fe->demodulator_priv;
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u8 quality = ~ves1820_readreg(state, 0x18);
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*snr = (quality << 8) | quality;
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return 0;
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}
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static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
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{
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struct ves1820_state* state = fe->demodulator_priv;
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*ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
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if (*ucblocks == 0x7f)
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*ucblocks = 0xffffffff;
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/* reset uncorrected block counter */
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ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
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ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
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return 0;
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}
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static int ves1820_get_frontend(struct dvb_frontend *fe)
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{
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struct dtv_frontend_properties *p = &fe->dtv_property_cache;
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struct ves1820_state* state = fe->demodulator_priv;
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int sync;
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s8 afc = 0;
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sync = ves1820_readreg(state, 0x11);
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afc = ves1820_readreg(state, 0x19);
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if (verbose) {
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/* AFC only valid when carrier has been recovered */
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printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
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"ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->symbol_rate * afc) >> 10);
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}
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if (!state->config->invert) {
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p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
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} else {
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p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
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}
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p->modulation = ((state->reg0 >> 2) & 7) + QAM_16;
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p->fec_inner = FEC_NONE;
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p->frequency = ((p->frequency + 31250) / 62500) * 62500;
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if (sync & 2)
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p->frequency -= ((s32) p->symbol_rate * afc) >> 10;
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return 0;
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}
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static int ves1820_sleep(struct dvb_frontend* fe)
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{
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struct ves1820_state* state = fe->demodulator_priv;
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ves1820_writereg(state, 0x1b, 0x02); /* pdown ADC */
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ves1820_writereg(state, 0x00, 0x80); /* standby */
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return 0;
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}
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static int ves1820_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
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{
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fesettings->min_delay_ms = 200;
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fesettings->step_size = 0;
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fesettings->max_drift = 0;
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return 0;
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}
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static void ves1820_release(struct dvb_frontend* fe)
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{
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struct ves1820_state* state = fe->demodulator_priv;
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kfree(state);
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}
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static struct dvb_frontend_ops ves1820_ops;
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struct dvb_frontend* ves1820_attach(const struct ves1820_config* config,
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struct i2c_adapter* i2c,
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u8 pwm)
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{
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struct ves1820_state* state = NULL;
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/* allocate memory for the internal state */
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state = kzalloc(sizeof(struct ves1820_state), GFP_KERNEL);
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if (state == NULL)
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goto error;
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/* setup the state */
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state->reg0 = ves1820_inittab[0];
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state->config = config;
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state->i2c = i2c;
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state->pwm = pwm;
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/* check if the demod is there */
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if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
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goto error;
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if (verbose)
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printk("ves1820: pwm=0x%02x\n", state->pwm);
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/* create dvb_frontend */
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memcpy(&state->frontend.ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
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state->frontend.ops.info.symbol_rate_min = (state->config->xin / 2) / 64; /* SACLK/64 == (XIN/2)/64 */
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state->frontend.ops.info.symbol_rate_max = (state->config->xin / 2) / 4; /* SACLK/4 */
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state->frontend.demodulator_priv = state;
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return &state->frontend;
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error:
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kfree(state);
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return NULL;
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}
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static struct dvb_frontend_ops ves1820_ops = {
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.delsys = { SYS_DVBC_ANNEX_A },
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.info = {
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.name = "VLSI VES1820 DVB-C",
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.frequency_stepsize = 62500,
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.frequency_min = 47000000,
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.frequency_max = 862000000,
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.caps = FE_CAN_QAM_16 |
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FE_CAN_QAM_32 |
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FE_CAN_QAM_64 |
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FE_CAN_QAM_128 |
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FE_CAN_QAM_256 |
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FE_CAN_FEC_AUTO
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},
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.release = ves1820_release,
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.init = ves1820_init,
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.sleep = ves1820_sleep,
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.set_frontend = ves1820_set_parameters,
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.get_frontend = ves1820_get_frontend,
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.get_tune_settings = ves1820_get_tune_settings,
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.read_status = ves1820_read_status,
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.read_ber = ves1820_read_ber,
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.read_signal_strength = ves1820_read_signal_strength,
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.read_snr = ves1820_read_snr,
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.read_ucblocks = ves1820_read_ucblocks,
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};
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module_param(verbose, int, 0644);
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MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
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MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
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MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
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MODULE_LICENSE("GPL");
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EXPORT_SYMBOL(ves1820_attach);
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