51ce30684e
This is an sh2a device with FPU, video display controller (VDC), 8 serial ports, 3 I2C channels, 2 CAN ports, SD and on-chip USB. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
153 lines
3.9 KiB
C
153 lines
3.9 KiB
C
/*
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* arch/sh/kernel/cpu/sh2a/clock-sh7264.c
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*
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* SH7264 clock framework support
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*
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* Copyright (C) 2012 Phil Edworthy
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/clkdev.h>
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#include <asm/clock.h>
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/* SH7264 registers */
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#define FRQCR 0xfffe0010
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#define STBCR3 0xfffe0408
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#define STBCR4 0xfffe040c
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#define STBCR5 0xfffe0410
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#define STBCR6 0xfffe0414
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#define STBCR7 0xfffe0418
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#define STBCR8 0xfffe041c
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static const unsigned int pll1rate[] = {8, 12};
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static unsigned int pll1_div;
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/* Fixed 32 KHz root clock for RTC */
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static struct clk r_clk = {
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.rate = 32768,
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};
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.rate = 18000000,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long rate = clk->parent->rate / pll1_div;
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return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];
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}
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static struct sh_clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.ops = &pll_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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struct clk *main_clks[] = {
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&r_clk,
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&extal_clk,
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&pll_clk,
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};
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static int div2[] = { 1, 2, 3, 4, 6, 8, 12 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_P,
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DIV4_NR };
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#define DIV4(_reg, _bit, _mask, _flags) \
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SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
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/* The mask field specifies the div2 entries that are valid */
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_I] = DIV4(FRQCR, 4, 0x7, CLK_ENABLE_REG_16BIT
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| CLK_ENABLE_ON_INIT),
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[DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
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};
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enum { MSTP77, MSTP74, MSTP72,
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MSTP60,
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MSTP35, MSTP34, MSTP33, MSTP32, MSTP30,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
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[MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
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[MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
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[MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
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[MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
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[MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
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[MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */
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[MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
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[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("rclk", &r_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("pll_clk", &pll_clk),
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/* DIV4 clocks */
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
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/* MSTP clocks */
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CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
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CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
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CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
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CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
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CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
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CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
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CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
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CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
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CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
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};
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int __init arch_clk_init(void)
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{
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int k, ret = 0;
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if (test_mode_pin(MODE_PIN0)) {
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if (test_mode_pin(MODE_PIN1))
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pll1_div = 3;
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else
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pll1_div = 4;
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} else
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pll1_div = 1;
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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return ret;
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}
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