3a0310eb36
Our uses of inline asm constraints for atomic operations are fairly
wild and varied. We basically need to guarantee the following:
1. Any instructions with barrier implications
(load-acquire/store-release) have a "memory" clobber
2. When performing exclusive accesses, the addresing mode is generated
using the "Q" constraint
3. Atomic blocks which use the condition flags, have a "cc" clobber
This patch addresses these concerns which, as well as fixing the
semantics of the code, stops GCC complaining about impossible asm
constraints.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
202 lines
4.5 KiB
C
202 lines
4.5 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/spinlock_types.h>
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#include <asm/processor.h>
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/*
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* Spinlock implementation.
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*
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* The old value is read exclusively and the new one, if unlocked, is written
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* exclusively. In case of failure, the loop is restarted.
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*
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* The memory barriers are implicit with the load-acquire and store-release
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* instructions.
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*
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* Unlocked value: 0
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* Locked value: 1
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*/
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#define arch_spin_is_locked(x) ((x)->lock != 0)
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#define arch_spin_unlock_wait(lock) \
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do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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asm volatile(
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" sevl\n"
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"1: wfe\n"
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"2: ldaxr %w0, %1\n"
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" cbnz %w0, 1b\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 2b\n"
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: "=&r" (tmp), "+Q" (lock->lock)
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: "r" (1)
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: "cc", "memory");
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int tmp;
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asm volatile(
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" ldaxr %w0, %1\n"
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" cbnz %w0, 1f\n"
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" stxr %w0, %w2, %1\n"
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"1:\n"
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: "=&r" (tmp), "+Q" (lock->lock)
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: "r" (1)
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: "cc", "memory");
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return !tmp;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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asm volatile(
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" stlr %w1, %0\n"
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: "=Q" (lock->lock) : "r" (0) : "memory");
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}
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/*
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* Write lock implementation.
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*
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* Write locks set bit 31. Unlocking, is done by writing 0 since the lock is
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* exclusively held.
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*
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* The memory barriers are implicit with the load-acquire and store-release
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* instructions.
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*/
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned int tmp;
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asm volatile(
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" sevl\n"
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"1: wfe\n"
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"2: ldaxr %w0, %1\n"
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" cbnz %w0, 1b\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 2b\n"
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: "=&r" (tmp), "+Q" (rw->lock)
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: "r" (0x80000000)
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: "cc", "memory");
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned int tmp;
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asm volatile(
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" ldaxr %w0, %1\n"
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" cbnz %w0, 1f\n"
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" stxr %w0, %w2, %1\n"
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"1:\n"
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: "=&r" (tmp), "+Q" (rw->lock)
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: "r" (0x80000000)
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: "cc", "memory");
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return !tmp;
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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asm volatile(
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" stlr %w1, %0\n"
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: "=Q" (rw->lock) : "r" (0) : "memory");
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}
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/* write_can_lock - would write_trylock() succeed? */
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#define arch_write_can_lock(x) ((x)->lock == 0)
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/*
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* Read lock implementation.
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*
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* It exclusively loads the lock value, increments it and stores the new value
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* back if positive and the CPU still exclusively owns the location. If the
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* value is negative, the lock is already held.
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*
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* During unlocking there may be multiple active read locks but no write lock.
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*
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* The memory barriers are implicit with the load-acquire and store-release
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* instructions.
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned int tmp, tmp2;
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asm volatile(
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" sevl\n"
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"1: wfe\n"
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"2: ldaxr %w0, %2\n"
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" add %w0, %w0, #1\n"
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" tbnz %w0, #31, 1b\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 2b\n"
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
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:
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: "cc", "memory");
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned int tmp, tmp2;
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asm volatile(
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"1: ldxr %w0, %2\n"
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" sub %w0, %w0, #1\n"
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" stlxr %w1, %w0, %2\n"
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" cbnz %w1, 1b\n"
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
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:
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: "cc", "memory");
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}
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned int tmp, tmp2 = 1;
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asm volatile(
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" ldaxr %w0, %2\n"
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" add %w0, %w0, #1\n"
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" tbnz %w0, #31, 1f\n"
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" stxr %w1, %w0, %2\n"
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"1:\n"
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: "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
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:
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: "cc", "memory");
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return !tmp2;
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}
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/* read_can_lock - would read_trylock() succeed? */
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#define arch_read_can_lock(x) ((x)->lock < 0x80000000)
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#endif /* __ASM_SPINLOCK_H */
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