4f04d8f005
The virtual memory layout is described in Documentation/arm64/memory.txt. This patch adds the MMU definitions for the 4KB and 64KB translation table configurations. The SECTION_SIZE is 2MB with 4KB page and 512MB with 64KB page configuration. PHYS_OFFSET is calculated at run-time and stored in a variable (no run-time code patching at this stage). On the current implementation, both user and kernel address spaces are 512G (39-bit) each with a maximum of 256G for the RAM linear mapping. Linux uses 3 levels of translation tables with the 4K page configuration and 2 levels with the 64K configuration. Extending the memory space beyond 39-bit with the 4K pages or 42-bit with 64K pages requires an additional level of translation tables. The SPARSEMEM configuration is global to all AArch64 platforms and allows for 1GB sections with SPARSEMEM_VMEMMAP enabled by default. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
50 lines
1.6 KiB
C
50 lines
1.6 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PGTABLE_3LEVEL_HWDEF_H
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#define __ASM_PGTABLE_3LEVEL_HWDEF_H
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/*
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* With LPAE and 4KB pages, there are 3 levels of page tables. Each level has
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* 512 entries of 8 bytes each, occupying a 4K page. The first level table
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* covers a range of 512GB, each entry representing 1GB. The user and kernel
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* address spaces are limited to 512GB each.
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*/
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#define PTRS_PER_PTE 512
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#define PTRS_PER_PMD 512
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#define PTRS_PER_PGD 512
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/*
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* PGDIR_SHIFT determines the size a top-level page table entry can map.
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*/
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#define PGDIR_SHIFT 30
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#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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/*
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* PMD_SHIFT determines the size a middle-level page table entry can map.
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*/
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#define PMD_SHIFT 21
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#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/*
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* section address mask and size definitions.
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*/
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#define SECTION_SHIFT 21
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#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
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#define SECTION_MASK (~(SECTION_SIZE-1))
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#endif
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