8ec6d93508
Add support for the Lantiq XWAY family of Mips24KEc SoCs.
* Danube (PSB50702)
* Twinpass (PSB4000)
* AR9 (PSB50802)
* Amazon SE (PSB5061)
The Amazon SE is a lightweight SoC and has no PCI as well as a different
clock. We split the code out into seperate files to handle this.
The GPIO pins on the SoCs are multi function and there are several bits
we can use to configure the pins. To be as compatible as possible to
GPIOLIB we add a function
int lq_gpio_request(unsigned int pin, unsigned int alt0,
unsigned int alt1, unsigned int dir, const char *name);
which lets you configure the 2 "alternate function" bits. This way drivers like
PCI can make use of GPIOLIB without a cubersome wrapper.
The PLL code inside arch/mips/lantiq/xway/clk-xway.c is voodoo to me. It was
taken from a 2.4.20 source tree and was never really changed by me since then.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2249/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
66 lines
2.4 KiB
C
66 lines
2.4 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2010 John Crispin <blogic@openwrt.org>
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*/
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#ifndef _LANTIQ_XWAY_IRQ_H__
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#define _LANTIQ_XWAY_IRQ_H__
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#define INT_NUM_IRQ0 8
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#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0)
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#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32)
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#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64)
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#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96)
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#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
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#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
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#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
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#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
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#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
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#define LTQ_ASC_ASE_TIR INT_NUM_IM2_IRL0
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#define LTQ_ASC_ASE_RIR (INT_NUM_IM2_IRL0 + 2)
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#define LTQ_ASC_ASE_EIR (INT_NUM_IM2_IRL0 + 3)
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#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
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#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
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#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
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#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
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#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
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#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
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#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
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#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
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#define MIPS_CPU_TIMER_IRQ 7
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#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
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#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
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#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
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#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
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#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
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#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
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#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
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#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
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#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
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#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
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#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
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#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
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#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
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#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
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#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
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#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
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#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
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#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
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#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
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#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
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#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
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#endif
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