bc6b92f8c3
Since the on-chip L1 regions are not cacheable, there is no point in trying to flush/invalidate them. Plus, older Blackfin parts like to trigger an exception (like BF533-0.3). Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
118 lines
3.8 KiB
C
118 lines
3.8 KiB
C
/*
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* Blackfin low-level cache routines
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*
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _BLACKFIN_CACHEFLUSH_H
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#define _BLACKFIN_CACHEFLUSH_H
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#include <asm/blackfin.h> /* for SSYNC() */
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#include <asm/sections.h> /* for _ramend */
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#ifdef CONFIG_SMP
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#include <asm/smp.h>
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#endif
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extern void blackfin_icache_flush_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dcache_flush_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dcache_invalidate_range(unsigned long start_address, unsigned long end_address);
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extern void blackfin_dflush_page(void *page);
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extern void blackfin_invalidate_entire_dcache(void);
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extern void blackfin_invalidate_entire_icache(void);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_cache_mm(mm) do { } while (0)
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#define flush_cache_range(vma, start, end) do { } while (0)
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#define flush_cache_page(vma, vmaddr) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#ifdef CONFIG_SMP
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#define flush_icache_range_others(start, end) \
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smp_icache_flush_range_others((start), (end))
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#else
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#define flush_icache_range_others(start, end) do { } while (0)
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#endif
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static inline void flush_icache_range(unsigned start, unsigned end)
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{
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
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if (end <= physical_mem_end)
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blackfin_dcache_flush_range(start, end);
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#endif
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#if defined(CONFIG_BFIN_L2_WRITEBACK)
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if (start >= L2_START && end <= L2_START + L2_LENGTH)
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blackfin_dcache_flush_range(start, end);
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#endif
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/* Make sure all write buffers in the data side of the core
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* are flushed before trying to invalidate the icache. This
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* needs to be after the data flush and before the icache
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* flush so that the SSYNC does the right thing in preventing
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* the instruction prefetcher from hitting things in cached
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* memory at the wrong time -- it runs much further ahead than
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* the pipeline.
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*/
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SSYNC();
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#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
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if (end <= physical_mem_end) {
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blackfin_icache_flush_range(start, end);
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flush_icache_range_others(start, end);
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}
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#endif
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#if defined(CONFIG_BFIN_L2_ICACHEABLE)
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if (start >= L2_START && end <= L2_START + L2_LENGTH) {
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blackfin_icache_flush_range(start, end);
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flush_icache_range_others(start, end);
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}
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#endif
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}
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { memcpy(dst, src, len); \
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flush_icache_range((unsigned) (dst), (unsigned) (dst) + (len)); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) memcpy(dst, src, len)
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#if defined(CONFIG_BFIN_DCACHE)
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# define invalidate_dcache_range(start,end) blackfin_dcache_invalidate_range((start), (end))
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#else
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# define invalidate_dcache_range(start,end) do { } while (0)
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#endif
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
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# define flush_dcache_range(start,end) blackfin_dcache_flush_range((start), (end))
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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# define flush_dcache_page(page) blackfin_dflush_page(page_address(page))
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#else
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# define flush_dcache_range(start,end) do { } while (0)
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 0
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# define flush_dcache_page(page) do { } while (0)
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#endif
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extern unsigned long reserved_mem_dcache_on;
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extern unsigned long reserved_mem_icache_on;
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static inline int bfin_addr_dcacheable(unsigned long addr)
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{
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#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
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if (addr < (_ramend - DMA_UNCACHED_REGION))
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return 1;
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#endif
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if (reserved_mem_dcache_on &&
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addr >= _ramend && addr < physical_mem_end)
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return 1;
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#ifdef CONFIG_BFIN_L2_DCACHEABLE
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if (addr >= L2_START && addr < L2_START + L2_LENGTH)
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return 1;
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#endif
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return 0;
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}
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#endif /* _BLACKFIN_ICACHEFLUSH_H */
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