b85a3ef4ac
The 1st board support is minimal to get a system up and running on the Xilinx platform. This platform reuses the clock implementation from plat-versatile, and it depends entirely on CONFIG_OF support. There is only one board support file which obtains all device information from a device tree dtb file which is passed to the kernel at boot time. Signed-off-by: John Linn <john.linn@xilinx.com>
48 lines
1.4 KiB
C
48 lines
1.4 KiB
C
/* arch/arm/mach-zynq/include/mach/zynq_soc.h
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*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_XILINX_SOC_H__
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#define __MACH_XILINX_SOC_H__
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#define PERIPHERAL_CLOCK_RATE 2500000
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/* For now, all mappings are flat (physical = virtual)
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*/
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#define UART0_PHYS 0xE0000000
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#define UART0_VIRT UART0_PHYS
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#define TTC0_PHYS 0xF8001000
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#define TTC0_VIRT TTC0_PHYS
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#define PL310_L2CC_PHYS 0xF8F02000
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#define PL310_L2CC_VIRT PL310_L2CC_PHYS
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#define SCU_PERIPH_PHYS 0xF8F00000
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#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS
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/* The following are intended for the devices that are mapped early */
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#define TTC0_BASE IOMEM(TTC0_VIRT)
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#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
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#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100)
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#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000)
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#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT)
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/*
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* Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
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*/
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#define LL_UART_PADDR UART0_PHYS
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#define LL_UART_VADDR UART0_VIRT
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#endif
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