d8000beef2
While playing with the out-of-tree MAE driver module, the system would panic after a while in the db1200 custom wait code after wakeup due to a clobbered k0 register being used as target address of a store op. Remove the custom wait implementation and revert back to the Alchemy- recommended implementation already set as default. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1092/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
78 lines
2.2 KiB
C
78 lines
2.2 KiB
C
/*
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* Alchemy/AMD/RMI DB1200 board setup.
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*
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* Licensed under the terms outlined in the file COPYING in the root of
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* this source archive.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include <asm/mach-db1x00/db1200.h>
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const char *get_system_type(void)
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{
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return "Alchemy Db1200";
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}
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void __init board_setup(void)
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{
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unsigned long freq0, clksrc, div, pfc;
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unsigned short whoami;
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bcsr_init(DB1200_BCSR_PHYS_ADDR,
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DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
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whoami = bcsr_read(BCSR_WHOAMI);
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printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
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" Board-ID %d Daughtercard ID %d\n",
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(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
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/* SMBus/SPI on PSC0, Audio on PSC1 */
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pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
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pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
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pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
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pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
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__raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
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wmb();
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/* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
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* CPU clock; all other clock generators off/unused.
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*/
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div = (get_au1x00_speed() + 25000000) / 50000000;
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if (div & 1)
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div++;
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div = ((div >> 1) - 1) & 0xff;
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freq0 = div << SYS_FC_FRDIV0_BIT;
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__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
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wmb();
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freq0 |= SYS_FC_FE0; /* enable F0 */
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__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
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wmb();
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/* psc0_intclk comes 1:1 from F0 */
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clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
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__raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
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wmb();
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}
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static int __init db1200_arch_init(void)
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{
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/* GPIO7 is low-level triggered CPLD cascade */
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set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
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bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
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/* do not autoenable these: CPLD has broken edge int handling,
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* and the CD handler setup requires manual enabling to work
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* around that.
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*/
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irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
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irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
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return 0;
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}
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arch_initcall(db1200_arch_init);
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