7b6d864b48
Preparing to move the parsing of reboot= to generic kernel code forces the change in reboot_mode handling to use the enum. [akpm@linux-foundation.org: fix arch/arm/mach-socfpga/socfpga.c] Signed-off-by: Robin Holt <holt@sgi.com> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Russ Anderson <rja@sgi.com> Cc: Robin Holt <holt@sgi.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
91 lines
2.3 KiB
C
91 lines
2.3 KiB
C
/*
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* reset controller for CSR SiRFprimaII
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/reboot.h>
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void __iomem *sirfsoc_rstc_base;
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static DEFINE_MUTEX(rstc_lock);
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static struct of_device_id rstc_ids[] = {
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{ .compatible = "sirf,prima2-rstc" },
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{ .compatible = "sirf,marco-rstc" },
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{},
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};
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static int __init sirfsoc_of_rstc_init(void)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, rstc_ids);
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if (!np) {
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pr_err("unable to find compatible sirf rstc node in dtb\n");
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return -ENOENT;
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}
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sirfsoc_rstc_base = of_iomap(np, 0);
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if (!sirfsoc_rstc_base)
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panic("unable to map rstc cpu registers\n");
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of_node_put(np);
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return 0;
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}
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early_initcall(sirfsoc_of_rstc_init);
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int sirfsoc_reset_device(struct device *dev)
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{
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u32 reset_bit;
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if (of_property_read_u32(dev->of_node, "reset-bit", &reset_bit))
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return -EINVAL;
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mutex_lock(&rstc_lock);
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if (of_device_is_compatible(dev->of_node, "sirf,prima2-rstc")) {
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/*
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* Writing 1 to this bit resets corresponding block. Writing 0 to this
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* bit de-asserts reset signal of the corresponding block.
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* datasheet doesn't require explicit delay between the set and clear
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* of reset bit. it could be shorter if tests pass.
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*/
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writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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msleep(10);
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writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
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sirfsoc_rstc_base + (reset_bit / 32) * 4);
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} else {
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/*
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* For MARCO and POLO
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* Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
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* register de-asserts reset signal of the corresponding block.
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* datasheet doesn't require explicit delay between the set and clear
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* of reset bit. it could be shorter if tests pass.
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*/
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writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
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msleep(10);
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writel(reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
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}
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mutex_unlock(&rstc_lock);
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return 0;
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}
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#define SIRFSOC_SYS_RST_BIT BIT(31)
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void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
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{
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writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
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}
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