68d00bbebb
Explicitly merging these two branches due to nontrivial conflicts and to allow further work. Resolved Conflicts: arch/x86/kernel/head32.c arch/x86/kernel/head64.c arch/x86/mm/init_64.c arch/x86/realmode/init.c Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
#include <linux/io.h>
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#include <linux/memblock.h>
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#include <asm/cacheflush.h>
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#include <asm/pgtable.h>
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#include <asm/realmode.h>
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struct real_mode_header *real_mode_header;
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u32 *trampoline_cr4_features;
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void __init reserve_real_mode(void)
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{
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phys_addr_t mem;
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unsigned char *base;
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size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);
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/* Has to be under 1M so we can execute real-mode AP code. */
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mem = memblock_find_in_range(0, 1<<20, size, PAGE_SIZE);
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if (!mem)
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panic("Cannot allocate trampoline\n");
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base = __va(mem);
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memblock_reserve(mem, size);
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real_mode_header = (struct real_mode_header *) base;
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printk(KERN_DEBUG "Base memory trampoline at [%p] %llx size %zu\n",
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base, (unsigned long long)mem, size);
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}
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void __init setup_real_mode(void)
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{
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u16 real_mode_seg;
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u32 *rel;
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u32 count;
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u32 *ptr;
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u16 *seg;
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int i;
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unsigned char *base;
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struct trampoline_header *trampoline_header;
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size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);
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#ifdef CONFIG_X86_64
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u64 *trampoline_pgd;
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u64 efer;
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#endif
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base = (unsigned char *)real_mode_header;
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memcpy(base, real_mode_blob, size);
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real_mode_seg = __pa(base) >> 4;
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rel = (u32 *) real_mode_relocs;
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/* 16-bit segment relocations. */
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count = rel[0];
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rel = &rel[1];
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for (i = 0; i < count; i++) {
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seg = (u16 *) (base + rel[i]);
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*seg = real_mode_seg;
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}
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/* 32-bit linear relocations. */
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count = rel[i];
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rel = &rel[i + 1];
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for (i = 0; i < count; i++) {
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ptr = (u32 *) (base + rel[i]);
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*ptr += __pa(base);
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}
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/* Must be perfomed *after* relocation. */
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trampoline_header = (struct trampoline_header *)
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__va(real_mode_header->trampoline_header);
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#ifdef CONFIG_X86_32
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trampoline_header->start = __pa_symbol(startup_32_smp);
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trampoline_header->gdt_limit = __BOOT_DS + 7;
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trampoline_header->gdt_base = __pa_symbol(boot_gdt);
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#else
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/*
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* Some AMD processors will #GP(0) if EFER.LMA is set in WRMSR
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* so we need to mask it out.
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*/
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rdmsrl(MSR_EFER, efer);
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trampoline_header->efer = efer & ~EFER_LMA;
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trampoline_header->start = (u64) secondary_startup_64;
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trampoline_cr4_features = &trampoline_header->cr4;
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*trampoline_cr4_features = read_cr4();
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trampoline_pgd = (u64 *) __va(real_mode_header->trampoline_pgd);
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trampoline_pgd[0] = init_level4_pgt[pgd_index(__PAGE_OFFSET)].pgd;
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trampoline_pgd[511] = init_level4_pgt[511].pgd;
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#endif
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}
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/*
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* reserve_real_mode() gets called very early, to guarantee the
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* availability of low memory. This is before the proper kernel page
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* tables are set up, so we cannot set page permissions in that
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* function. Also trampoline code will be executed by APs so we
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* need to mark it executable at do_pre_smp_initcalls() at least,
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* thus run it as a early_initcall().
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*/
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static int __init set_real_mode_permissions(void)
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{
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unsigned char *base = (unsigned char *) real_mode_header;
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size_t size = PAGE_ALIGN(real_mode_blob_end - real_mode_blob);
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size_t ro_size =
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PAGE_ALIGN(real_mode_header->ro_end) -
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__pa(base);
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size_t text_size =
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PAGE_ALIGN(real_mode_header->ro_end) -
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real_mode_header->text_start;
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unsigned long text_start =
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(unsigned long) __va(real_mode_header->text_start);
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set_memory_nx((unsigned long) base, size >> PAGE_SHIFT);
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set_memory_ro((unsigned long) base, ro_size >> PAGE_SHIFT);
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set_memory_x((unsigned long) text_start, text_size >> PAGE_SHIFT);
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return 0;
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}
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early_initcall(set_real_mode_permissions);
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