81c6fdb653
Provide common mpc5121.dtsi file for mpc5121 SoC and modify mpc5121ads.dts to use mpc5121.dtsi. Signed-off-by: Anatolij Gustschin <agust@denx.de>
178 lines
3.6 KiB
Text
178 lines
3.6 KiB
Text
/*
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* MPC5121E ADS Device Tree Source
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*
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* Copyright 2007-2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "mpc5121.dtsi"
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/ {
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model = "mpc5121ads";
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compatible = "fsl,mpc5121ads";
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nfc@40000000 {
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/*
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* ADS has two Hynix 512MB Nand flash chips in a single
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* stacked package.
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*/
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chips = <2>;
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nand@0 {
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label = "nand";
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reg = <0x00000000 0x40000000>; /* 512MB + 512MB */
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};
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};
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localbus@80000020 {
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ranges = <0x0 0x0 0xfc000000 0x04000000
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0x2 0x0 0x82000000 0x00008000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0x0 0x4000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <4>;
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device-width = <2>;
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protected@0 {
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label = "protected";
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reg = <0x00000000 0x00040000>; // first sector is protected
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read-only;
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};
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filesystem@40000 {
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label = "filesystem";
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reg = <0x00040000 0x03c00000>; // 60M for filesystem
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};
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kernel@3c40000 {
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label = "kernel";
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reg = <0x03c40000 0x00280000>; // 2.5M for kernel
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};
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device-tree@3ec0000 {
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label = "device-tree";
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reg = <0x03ec0000 0x00040000>; // one sector for device tree
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};
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u-boot@3f00000 {
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label = "u-boot";
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reg = <0x03f00000 0x00100000>; // 1M for u-boot
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read-only;
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};
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};
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board-control@2,0 {
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compatible = "fsl,mpc5121ads-cpld";
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reg = <0x2 0x0 0x8000>;
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};
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cpld_pic: pic@2,a {
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compatible = "fsl,mpc5121ads-cpld-pic";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x2 0xa 0x5>;
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/* irq routing:
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* all irqs but touch screen are routed to irq0 (ipic 48)
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* touch screen is statically routed to irq1 (ipic 17)
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* so don't use it here
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*/
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interrupts = <48 0x8>;
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};
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};
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soc@80000000 {
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i2c@1700 {
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fsl,preserve-clocking;
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hwmon@4a {
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compatible = "adi,ad7414";
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reg = <0x4a>;
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};
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eeprom@50 {
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compatible = "at,24c32";
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reg = <0x50>;
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};
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rtc@68 {
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compatible = "stm,m41t62";
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reg = <0x68>;
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};
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};
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eth0: ethernet@2800 {
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phy-handle = <&phy0>;
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};
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can@2300 {
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status = "disabled";
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};
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can@2380 {
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status = "disabled";
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};
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viu@2400 {
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status = "disabled";
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};
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mdio@2800 {
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phy0: ethernet-phy@0 {
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reg = <1>;
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};
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};
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/* mpc5121ads only uses USB0 */
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usb@3000 {
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status = "disabled";
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};
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/* USB0 using internal UTMI PHY */
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usb@4000 {
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dr_mode = "host";
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fsl,invert-drvvbus;
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fsl,invert-pwr-fault;
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};
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/* PSC3 serial port A aka ttyPSC0 */
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psc@11300 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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};
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/* PSC4 serial port B aka ttyPSC1 */
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psc@11400 {
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
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};
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/* PSC5 in ac97 mode */
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ac97: psc@11500 {
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compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";
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fsl,mode = "ac97-slave";
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fsl,rx-fifo-size = <384>;
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fsl,tx-fifo-size = <384>;
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};
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};
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pci: pci@80008500 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x15 - Slot 1 PCI */
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0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8
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0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8
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0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8
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0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8
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/* IDSEL 0x16 - Slot 2 MiniPCI */
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0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8
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0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8
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/* IDSEL 0x17 - Slot 3 MiniPCI */
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0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8
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0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8
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>;
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};
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};
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