156 lines
		
	
	
	
		
			4.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			156 lines
		
	
	
	
		
			4.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * This file is subject to the terms and conditions of the GNU General Public
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|  * License.  See the file "COPYING" in the main directory of this archive
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|  * for more details.
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|  */
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| #ifndef _ASM_PCI_H
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| #define _ASM_PCI_H
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| 
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| #include <linux/mm.h>
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| 
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| #ifdef __KERNEL__
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| 
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| /*
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|  * This file essentially defines the interface between board
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|  * specific PCI code and MIPS common PCI code.	Should potentially put
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|  * into include/asm/pci.h file.
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|  */
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| 
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| #include <linux/ioport.h>
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| #include <linux/of.h>
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| 
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| /*
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|  * Each pci channel is a top-level PCI bus seem by CPU.	 A machine  with
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|  * multiple PCI channels may have multiple PCI host controllers or a
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|  * single controller supporting multiple channels.
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|  */
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| struct pci_controller {
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| 	struct pci_controller *next;
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| 	struct pci_bus *bus;
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| 	struct device_node *of_node;
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| 
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| 	struct pci_ops *pci_ops;
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| 	struct resource *mem_resource;
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| 	unsigned long mem_offset;
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| 	struct resource *io_resource;
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| 	unsigned long io_offset;
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| 	unsigned long io_map_base;
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| 
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| 	unsigned int index;
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| 	/* For compatibility with current (as of July 2003) pciutils
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| 	   and XFree86. Eventually will be removed. */
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| 	unsigned int need_domain_info;
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| 
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| 	int iommu;
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| 
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| 	/* Optional access methods for reading/writing the bus number
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| 	   of the PCI controller */
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| 	int (*get_busno)(void);
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| 	void (*set_busno)(int busno);
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| };
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| 
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| /*
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|  * Used by boards to register their PCI busses before the actual scanning.
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|  */
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| extern struct pci_controller * alloc_pci_controller(void);
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| extern void register_pci_controller(struct pci_controller *hose);
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| 
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| /*
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|  * board supplied pci irq fixup routine
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|  */
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| extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
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| 
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| 
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| /* Can be used to override the logic in pci_scan_bus for skipping
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|    already-configured bus numbers - to be used for buggy BIOSes
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|    or architectures with incomplete PCI setup by the loader */
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| 
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| extern unsigned int pcibios_assign_all_busses(void);
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| 
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| extern unsigned long PCIBIOS_MIN_IO;
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| extern unsigned long PCIBIOS_MIN_MEM;
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| 
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| #define PCIBIOS_MIN_CARDBUS_IO	0x4000
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| 
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| extern void pcibios_set_master(struct pci_dev *dev);
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| 
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| static inline void pcibios_penalize_isa_irq(int irq, int active)
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| {
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| 	/* We don't do dynamic PCI IRQ allocation */
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| }
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| 
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| #define HAVE_PCI_MMAP
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| 
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| extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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| 	enum pci_mmap_state mmap_state, int write_combine);
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| 
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| /*
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|  * Dynamic DMA mapping stuff.
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|  * MIPS has everything mapped statically.
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|  */
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| 
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| #include <linux/types.h>
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| #include <linux/slab.h>
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| #include <asm/scatterlist.h>
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| #include <linux/string.h>
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| #include <asm/io.h>
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| #include <asm-generic/pci-bridge.h>
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| 
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| struct pci_dev;
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| 
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| /*
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|  * The PCI address space does equal the physical memory address space.	The
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|  * networking and block device layers use this boolean for bounce buffer
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|  * decisions.  This is set if any hose does not have an IOMMU.
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|  */
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| extern unsigned int PCI_DMA_BUS_IS_PHYS;
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| 
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| #ifdef CONFIG_PCI
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| static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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| 					enum pci_dma_burst_strategy *strat,
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| 					unsigned long *strategy_parameter)
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| {
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| 	*strat = PCI_DMA_BURST_INFINITY;
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| 	*strategy_parameter = ~0UL;
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| }
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| #endif
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| 
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| #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
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| 
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| static inline int pci_proc_domain(struct pci_bus *bus)
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| {
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| 	struct pci_controller *hose = bus->sysdata;
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| 	return hose->need_domain_info;
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| }
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| 
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| #endif /* __KERNEL__ */
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| 
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| /* implement the pci_ DMA API in terms of the generic device dma_ one */
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| #include <asm-generic/pci-dma-compat.h>
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| 
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| /* Do platform specific device initialization at pci_enable_device() time */
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| extern int pcibios_plat_dev_init(struct pci_dev *dev);
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| 
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| /* Chances are this interrupt is wired PC-style ...  */
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| static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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| {
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| 	return channel ? 15 : 14;
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| }
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| 
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| #ifdef CONFIG_CPU_CAVIUM_OCTEON
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| /* MSI arch hook for OCTEON */
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| #define arch_setup_msi_irqs arch_setup_msi_irqs
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| #endif
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| 
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| extern char * (*pcibios_plat_setup)(char *str);
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| 
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| #ifdef CONFIG_OF
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| /* this function parses memory ranges from a device node */
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| extern void pci_load_of_ranges(struct pci_controller *hose,
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| 			       struct device_node *node);
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| #else
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| static inline void pci_load_of_ranges(struct pci_controller *hose,
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| 				      struct device_node *node) {}
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| #endif
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| 
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| #endif /* _ASM_PCI_H */
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