1c75c42100
From Dinh Nguyen, this is a series of patches introducing support for socfpga hardware (Altera Cyclone5). It also includes a cleanup that moves some of the ARMv7 cache maintenance functions to a common location, since three other platforms aready implemented it separately. * socfpga/hw: arm: socfpga: Add SMP support for actual socfpga harware arm: Add v7_invalidate_l1 to cache-v7.S arm: socfpga: Add entries to enable make dtbs socfpga arm: socfpga: Add new device tree source for actual socfpga HW Trivial conflict in arch/arm/mach-tegra/headsmp.S. Signed-off-by: Olof Johansson <olof@lixom.net>
117 lines
3.1 KiB
C
117 lines
3.1 KiB
C
/*
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* Copyright 2010-2011 Calxeda, Inc.
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* Copyright 2012 Pavel Machek <pavel@denx.de>
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* Based on platsmp.c, Copyright (C) 2002 ARM Ltd.
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* Copyright (C) 2012 Altera Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_plat.h>
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#include "core.h"
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extern void __iomem *sys_manager_base_addr;
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extern void __iomem *rst_manager_base_addr;
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static void __cpuinit socfpga_secondary_init(unsigned int cpu)
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{
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/*
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* if any interrupts are already enabled for the primary
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* core (e.g. timer irq), then they will not have been enabled
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* for us: do so
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*/
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gic_secondary_init(0);
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}
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static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
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if (cpu1start_addr) {
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memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
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__raw_writel(virt_to_phys(socfpga_secondary_startup),
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(sys_manager_base_addr + (cpu1start_addr & 0x000000ff)));
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flush_cache_all();
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smp_wmb();
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outer_clean_range(0, trampoline_size);
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/* This will release CPU #1 out of reset.*/
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__raw_writel(0, rst_manager_base_addr + 0x10);
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}
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init socfpga_smp_init_cpus(void)
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{
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unsigned int i, ncores;
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ncores = scu_get_core_count(socfpga_scu_base_addr);
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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/* sanity check */
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if (ncores > num_possible_cpus()) {
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pr_warn("socfpga: no. of cores (%d) greater than configured"
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"maximum of %d - clipping\n", ncores, num_possible_cpus());
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ncores = num_possible_cpus();
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(socfpga_scu_base_addr);
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}
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/*
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* platform-specific code to shutdown a CPU
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*
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* Called with IRQs disabled
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*/
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static void socfpga_cpu_die(unsigned int cpu)
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{
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cpu_do_idle();
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/* We should have never returned from idle */
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panic("cpu %d unexpectedly exit from shutdown\n", cpu);
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}
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struct smp_operations socfpga_smp_ops __initdata = {
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.smp_init_cpus = socfpga_smp_init_cpus,
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.smp_prepare_cpus = socfpga_smp_prepare_cpus,
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.smp_secondary_init = socfpga_secondary_init,
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.smp_boot_secondary = socfpga_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = socfpga_cpu_die,
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#endif
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};
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