6bb27d7349
Now that the only field in struct sys_timer is .init, delete the struct, and replace the machine descriptor .timer field with the initialization function itself. This will enable moving timer drivers into drivers/clocksource without having to place a public prototype of each struct sys_timer object into include/linux; the intent is to create a single of_clocksource_init() function that determines which timer driver to initialize by scanning the device dtree, much like the proposed irqchip_init() at: http://www.spinics.net/lists/arm-kernel/msg203686.html Includes mach-omap2 fixes from Igor Grinberg. Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
596 lines
19 KiB
C
596 lines
19 KiB
C
/*
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* linux/arch/arm/mach-at91/board-yl-9200.c
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*
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* Adapted from various board files in arch/arm/mach-at91
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*
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* Modifications for YL-9200 platform:
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* Copyright (C) 2007 S. Birtles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/types.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/ads7846.h>
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#include <linux/mtd/physmap.h>
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#include <linux/gpio_keys.h>
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#include <linux/input.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <mach/hardware.h>
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#include <mach/at91rm9200_mc.h>
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#include <mach/at91_ramc.h>
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#include <mach/cpu.h>
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#include "at91_aic.h"
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#include "board.h"
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#include "generic.h"
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static void __init yl9200_init_early(void)
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{
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/* Set cpu type: PQFP */
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at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
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/* Initialize processor: 18.432 MHz crystal */
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at91_initialize(18432000);
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}
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/*
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* LEDs
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*/
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static struct gpio_led yl9200_leds[] = {
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{ /* D2 */
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.name = "led2",
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.gpio = AT91_PIN_PB17,
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.active_low = 1,
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.default_trigger = "timer",
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},
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{ /* D3 */
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.name = "led3",
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.gpio = AT91_PIN_PB16,
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.active_low = 1,
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.default_trigger = "heartbeat",
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},
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{ /* D4 */
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.name = "led4",
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.gpio = AT91_PIN_PB15,
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.active_low = 1,
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},
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{ /* D5 */
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.name = "led5",
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.gpio = AT91_PIN_PB8,
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.active_low = 1,
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}
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};
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/*
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* Ethernet
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*/
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static struct macb_platform_data __initdata yl9200_eth_data = {
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.phy_irq_pin = AT91_PIN_PB28,
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.is_rmii = 1,
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};
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/*
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* USB Host
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*/
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static struct at91_usbh_data __initdata yl9200_usbh_data = {
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.ports = 1, /* PQFP version of AT91RM9200 */
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.vbus_pin = {-EINVAL, -EINVAL},
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.overcurrent_pin= {-EINVAL, -EINVAL},
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};
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/*
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* USB Device
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*/
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static struct at91_udc_data __initdata yl9200_udc_data = {
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.pullup_pin = AT91_PIN_PC4,
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.vbus_pin = AT91_PIN_PC5,
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.pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
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};
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/*
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* MMC
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*/
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static struct mci_platform_data __initdata yl9200_mci0_data = {
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.slot[0] = {
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.bus_width = 4,
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.detect_pin = AT91_PIN_PB9,
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.wp_pin = -EINVAL,
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},
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};
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/*
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* NAND Flash
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*/
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static struct mtd_partition __initdata yl9200_nand_partition[] = {
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{
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.name = "AT91 NAND partition 1, boot",
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.offset = 0,
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.size = SZ_256K
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},
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{
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.name = "AT91 NAND partition 2, kernel",
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.offset = MTDPART_OFS_NXTBLK,
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.size = (2 * SZ_1M) - SZ_256K
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},
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{
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.name = "AT91 NAND partition 3, filesystem",
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.offset = MTDPART_OFS_NXTBLK,
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.size = 14 * SZ_1M
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},
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{
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.name = "AT91 NAND partition 4, storage",
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.offset = MTDPART_OFS_NXTBLK,
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.size = SZ_16M
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},
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{
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.name = "AT91 NAND partition 5, ext-fs",
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.offset = MTDPART_OFS_NXTBLK,
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.size = SZ_32M
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}
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};
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static struct atmel_nand_data __initdata yl9200_nand_data = {
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.ale = 6,
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.cle = 7,
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.det_pin = -EINVAL,
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.rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
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.enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
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.ecc_mode = NAND_ECC_SOFT,
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.parts = yl9200_nand_partition,
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.num_parts = ARRAY_SIZE(yl9200_nand_partition),
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};
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/*
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* NOR Flash
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*/
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#define YL9200_FLASH_BASE AT91_CHIPSELECT_0
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#define YL9200_FLASH_SIZE SZ_16M
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static struct mtd_partition yl9200_flash_partitions[] = {
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{
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.name = "Bootloader",
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.offset = 0,
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.size = SZ_256K,
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.mask_flags = MTD_WRITEABLE, /* force read-only */
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},
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{
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.name = "Kernel",
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.offset = MTDPART_OFS_NXTBLK,
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.size = (2 * SZ_1M) - SZ_256K
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},
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{
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.name = "Filesystem",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL
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}
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};
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static struct physmap_flash_data yl9200_flash_data = {
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.width = 2,
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.parts = yl9200_flash_partitions,
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.nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
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};
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static struct resource yl9200_flash_resources[] = {
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{
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.start = YL9200_FLASH_BASE,
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.end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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static struct platform_device yl9200_flash = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &yl9200_flash_data,
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},
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.resource = yl9200_flash_resources,
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.num_resources = ARRAY_SIZE(yl9200_flash_resources),
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};
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/*
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* I2C (TWI)
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*/
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static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
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{ /* EEPROM */
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I2C_BOARD_INFO("24c128", 0x50),
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}
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};
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/*
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* GPIO Buttons
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*/
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#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
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static struct gpio_keys_button yl9200_buttons[] = {
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{
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.gpio = AT91_PIN_PA24,
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.code = BTN_2,
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.desc = "SW2",
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.active_low = 1,
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.wakeup = 1,
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},
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{
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.gpio = AT91_PIN_PB1,
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.code = BTN_3,
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.desc = "SW3",
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.active_low = 1,
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.wakeup = 1,
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},
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{
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.gpio = AT91_PIN_PB2,
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.code = BTN_4,
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.desc = "SW4",
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.active_low = 1,
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.wakeup = 1,
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},
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{
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.gpio = AT91_PIN_PB6,
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.code = BTN_5,
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.desc = "SW5",
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.active_low = 1,
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.wakeup = 1,
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}
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};
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static struct gpio_keys_platform_data yl9200_button_data = {
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.buttons = yl9200_buttons,
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.nbuttons = ARRAY_SIZE(yl9200_buttons),
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};
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static struct platform_device yl9200_button_device = {
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.name = "gpio-keys",
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.id = -1,
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.num_resources = 0,
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.dev = {
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.platform_data = &yl9200_button_data,
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}
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};
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static void __init yl9200_add_device_buttons(void)
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{
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at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
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at91_set_deglitch(AT91_PIN_PA24, 1);
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at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
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at91_set_deglitch(AT91_PIN_PB1, 1);
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at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
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at91_set_deglitch(AT91_PIN_PB2, 1);
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at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
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at91_set_deglitch(AT91_PIN_PB6, 1);
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/* Enable buttons (Sheet 5) */
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at91_set_gpio_output(AT91_PIN_PB7, 1);
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platform_device_register(&yl9200_button_device);
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}
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#else
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static void __init yl9200_add_device_buttons(void) {}
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#endif
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/*
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* Touchscreen
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*/
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#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
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static int ads7843_pendown_state(void)
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{
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return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
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}
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static struct ads7846_platform_data ads_info = {
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.model = 7843,
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.x_min = 150,
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.x_max = 3830,
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.y_min = 190,
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.y_max = 3830,
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.vref_delay_usecs = 100,
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/* For a 8" touch-screen */
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// .x_plate_ohms = 603,
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// .y_plate_ohms = 332,
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/* For a 10.4" touch-screen */
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// .x_plate_ohms = 611,
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// .y_plate_ohms = 325,
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.x_plate_ohms = 576,
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.y_plate_ohms = 366,
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.pressure_max = 15000, /* generally nonsense on the 7843 */
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.debounce_max = 1,
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.debounce_rep = 0,
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.debounce_tol = (~0),
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.get_pendown_state = ads7843_pendown_state,
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};
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static void __init yl9200_add_device_ts(void)
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{
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at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
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at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
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}
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#else
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static void __init yl9200_add_device_ts(void) {}
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#endif
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/*
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* SPI devices
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*/
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static struct spi_board_info yl9200_spi_devices[] = {
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#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
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{ /* Touchscreen */
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.modalias = "ads7846",
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.chip_select = 0,
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.max_speed_hz = 5000 * 26,
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.platform_data = &ads_info,
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.irq = AT91_PIN_PB11,
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},
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#endif
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{ /* CAN */
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.modalias = "mcp2510",
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.chip_select = 1,
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.max_speed_hz = 25000 * 26,
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.irq = AT91_PIN_PC0,
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}
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};
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/*
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* LCD / VGA
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*
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* EPSON S1D13806 FB (discontinued chip)
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* EPSON S1D13506 FB
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*/
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#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
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#include <video/s1d13xxxfb.h>
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static void yl9200_init_video(void)
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{
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/* NWAIT Signal */
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at91_set_A_periph(AT91_PIN_PC6, 0);
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/* Initialization of the Static Memory Controller for Chip Select 2 */
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at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
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| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
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| AT91_SMC_TDF_(0x100) /* float time */
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);
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}
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static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
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{
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{S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
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{S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
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{S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
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{S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
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{S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
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{S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
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{S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
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{S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
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{S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
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{S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
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{S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
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{S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
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{S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
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{S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
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{S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
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{S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
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{S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
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{S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
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{S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
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{S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
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{S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
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{S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
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{S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
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{S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
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{S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
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{S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
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{S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
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{S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
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{S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
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{S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
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{S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
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{S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
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{S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
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{S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
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{S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
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{S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
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{S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
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{S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
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{S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
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{S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
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{S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
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{S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
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{S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
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{S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
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{S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
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{S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
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{S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
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{S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
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{S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
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{S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
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{S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
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{S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
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{S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
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{S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
|
|
{S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
|
|
{S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
|
|
{S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
|
|
{S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
|
|
{S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
|
|
{S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
|
|
{S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
|
|
{S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
|
|
{S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
|
|
{S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
|
|
{S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
|
|
{S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
|
|
{S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
|
|
{S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
|
|
{S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
|
|
{S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
|
|
{S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
|
|
{S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
|
|
{S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
|
|
{S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
|
|
{S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
|
|
{S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
|
|
{S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
|
|
{S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
|
|
{S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
|
|
{S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
|
|
{S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
|
|
{S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
|
|
{S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
|
|
{S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
|
|
{S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
|
|
{S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
|
|
{S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
|
|
{S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
|
|
{S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
|
|
{S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
|
|
{S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
|
|
{S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
|
|
{S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
|
|
{S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
|
|
{S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
|
|
{S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
|
|
{S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
|
|
{S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
|
|
{S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
|
|
{S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
|
|
{S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
|
|
{S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
|
|
{S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
|
|
{S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
|
|
{S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
|
|
};
|
|
|
|
static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
|
|
.initregs = yl9200_s1dfb_initregs,
|
|
.initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
|
|
.platform_init_video = yl9200_init_video,
|
|
};
|
|
|
|
#define YL9200_FB_REG_BASE AT91_CHIPSELECT_7
|
|
#define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M
|
|
#define YL9200_FB_VMEM_SIZE SZ_2M
|
|
|
|
static struct resource yl9200_s1dfb_resource[] = {
|
|
[0] = { /* video mem */
|
|
.name = "s1d13xxxfb memory",
|
|
.start = YL9200_FB_VMEM_BASE,
|
|
.end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = { /* video registers */
|
|
.name = "s1d13xxxfb registers",
|
|
.start = YL9200_FB_REG_BASE,
|
|
.end = YL9200_FB_REG_BASE + SZ_512 -1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
};
|
|
|
|
static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
|
|
|
|
static struct platform_device yl9200_s1dfb_device = {
|
|
.name = "s1d13806fb",
|
|
.id = -1,
|
|
.dev = {
|
|
.dma_mask = &s1dfb_dmamask,
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &yl9200_s1dfb_pdata,
|
|
},
|
|
.resource = yl9200_s1dfb_resource,
|
|
.num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
|
|
};
|
|
|
|
void __init yl9200_add_device_video(void)
|
|
{
|
|
platform_device_register(&yl9200_s1dfb_device);
|
|
}
|
|
#else
|
|
void __init yl9200_add_device_video(void) {}
|
|
#endif
|
|
|
|
|
|
static void __init yl9200_board_init(void)
|
|
{
|
|
/* Serial */
|
|
/* DBGU on ttyS0. (Rx & Tx only) */
|
|
at91_register_uart(0, 0, 0);
|
|
|
|
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
|
|
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
|
|
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
|
|
| ATMEL_UART_RI);
|
|
|
|
/* USART0 on ttyS2. (Rx & Tx only to JP3) */
|
|
at91_register_uart(AT91RM9200_ID_US0, 2, 0);
|
|
|
|
/* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
|
|
at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
|
|
at91_add_device_serial();
|
|
/* Ethernet */
|
|
at91_add_device_eth(&yl9200_eth_data);
|
|
/* USB Host */
|
|
at91_add_device_usbh(&yl9200_usbh_data);
|
|
/* USB Device */
|
|
at91_add_device_udc(&yl9200_udc_data);
|
|
/* I2C */
|
|
at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
|
|
/* MMC */
|
|
at91_add_device_mci(0, &yl9200_mci0_data);
|
|
/* NAND */
|
|
at91_add_device_nand(&yl9200_nand_data);
|
|
/* NOR Flash */
|
|
platform_device_register(&yl9200_flash);
|
|
#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
|
|
/* SPI */
|
|
at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
|
|
/* Touchscreen */
|
|
yl9200_add_device_ts();
|
|
#endif
|
|
/* LEDs. */
|
|
at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
|
|
/* Push Buttons */
|
|
yl9200_add_device_buttons();
|
|
/* VGA */
|
|
yl9200_add_device_video();
|
|
}
|
|
|
|
MACHINE_START(YL9200, "uCdragon YL-9200")
|
|
/* Maintainer: S.Birtles */
|
|
.init_time = at91rm9200_timer_init,
|
|
.map_io = at91_map_io,
|
|
.handle_irq = at91_aic_handle_irq,
|
|
.init_early = yl9200_init_early,
|
|
.init_irq = at91_init_irq_default,
|
|
.init_machine = yl9200_board_init,
|
|
MACHINE_END
|