c54a169b52
This patch adds a separate ioctl for delivering syncpoint base number to user space. If the syncpoint does not have an associated base, the function returns -ENXIO. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
149 lines
3.7 KiB
C
149 lines
3.7 KiB
C
/*
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* Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _UAPI_TEGRA_DRM_H_
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#define _UAPI_TEGRA_DRM_H_
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#include <drm/drm.h>
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#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
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#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
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struct drm_tegra_gem_create {
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__u64 size;
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__u32 flags;
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__u32 handle;
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};
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struct drm_tegra_gem_mmap {
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__u32 handle;
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__u32 offset;
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};
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struct drm_tegra_syncpt_read {
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__u32 id;
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__u32 value;
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};
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struct drm_tegra_syncpt_incr {
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__u32 id;
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__u32 pad;
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};
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struct drm_tegra_syncpt_wait {
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__u32 id;
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__u32 thresh;
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__u32 timeout;
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__u32 value;
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};
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#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
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struct drm_tegra_open_channel {
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__u32 client;
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__u32 pad;
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__u64 context;
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};
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struct drm_tegra_close_channel {
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__u64 context;
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};
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struct drm_tegra_get_syncpt {
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__u64 context;
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__u32 index;
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__u32 id;
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};
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struct drm_tegra_get_syncpt_base {
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__u64 context;
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__u32 syncpt;
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__u32 id;
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};
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struct drm_tegra_syncpt {
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__u32 id;
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__u32 incrs;
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};
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struct drm_tegra_cmdbuf {
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__u32 handle;
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__u32 offset;
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__u32 words;
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__u32 pad;
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};
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struct drm_tegra_reloc {
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struct {
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__u32 handle;
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__u32 offset;
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} cmdbuf;
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struct {
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__u32 handle;
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__u32 offset;
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} target;
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__u32 shift;
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__u32 pad;
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};
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struct drm_tegra_waitchk {
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__u32 handle;
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__u32 offset;
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__u32 syncpt;
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__u32 thresh;
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};
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struct drm_tegra_submit {
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__u64 context;
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__u32 num_syncpts;
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__u32 num_cmdbufs;
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__u32 num_relocs;
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__u32 num_waitchks;
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__u32 waitchk_mask;
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__u32 timeout;
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__u32 pad;
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__u64 syncpts;
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__u64 cmdbufs;
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__u64 relocs;
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__u64 waitchks;
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__u32 fence; /* Return value */
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__u32 reserved[5]; /* future expansion */
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};
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#define DRM_TEGRA_GEM_CREATE 0x00
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#define DRM_TEGRA_GEM_MMAP 0x01
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#define DRM_TEGRA_SYNCPT_READ 0x02
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#define DRM_TEGRA_SYNCPT_INCR 0x03
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#define DRM_TEGRA_SYNCPT_WAIT 0x04
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#define DRM_TEGRA_OPEN_CHANNEL 0x05
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#define DRM_TEGRA_CLOSE_CHANNEL 0x06
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#define DRM_TEGRA_GET_SYNCPT 0x07
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#define DRM_TEGRA_SUBMIT 0x08
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#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
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#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
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#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
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#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
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#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
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#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
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#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
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#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
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#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
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#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
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#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
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#endif
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