638ee2db19
add csp chipc block source code Signed-off-by: Leo Chen <leochen@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
293 lines
9.3 KiB
C
293 lines
9.3 KiB
C
/*****************************************************************************
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* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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/****************************************************************************/
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/**
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* @file chipcHw_init.c
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*
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* @brief Low level CHIPC PLL configuration functions
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*
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* @note
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*
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* These routines provide basic PLL controlling functionality only.
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*/
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/****************************************************************************/
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/* ---- Include Files ---------------------------------------------------- */
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#include <csp/errno.h>
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#include <csp/stdint.h>
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#include <csp/module.h>
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#include <mach/csp/chipcHw_def.h>
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#include <mach/csp/chipcHw_inline.h>
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#include <csp/reg.h>
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#include <csp/delay.h>
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/* ---- Private Constants and Types --------------------------------------- */
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/*
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Calculation for NDIV_i to obtain VCO frequency
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-----------------------------------------------
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Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
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for Freq_vco = VCO_FREQ_MHz
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Freq_ref = chipcHw_XTAL_FREQ_Hz
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PLL_P1 = PLL_P2 = 1
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and
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PLL_NDIV_f = 0
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We get:
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PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
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Calculation for PLL MDIV to obtain frequency Freq_x for channel x
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-----------------------------------------------------------------
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Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
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PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
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*/
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/* ---- Private Variables ------------------------------------------------- */
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/****************************************************************************/
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/**
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* @brief Initializes the PLL2
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*
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* This function initializes the PLL2
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*
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*/
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/****************************************************************************/
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void chipcHw_pll2Enable(uint32_t vcoFreqHz)
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{
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uint32_t pllPreDivider2 = 0;
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{
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REG_LOCAL_IRQ_SAVE;
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pChipcHw->PLLConfig2 =
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chipcHw_REG_PLL_CONFIG_D_RESET |
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chipcHw_REG_PLL_CONFIG_A_RESET;
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pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
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chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
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(chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
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chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
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(chipcHw_REG_PLL_PREDIVIDER_P1 <<
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chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
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(chipcHw_REG_PLL_PREDIVIDER_P2 <<
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chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
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/* Enable CHIPC registers to control the PLL */
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pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
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/* Set pre divider to get desired VCO frequency */
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pChipcHw->PLLPreDivider2 = pllPreDivider2;
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/* Set NDIV Frac */
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pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
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/* This has to be removed once the default values are fixed for PLL2. */
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pChipcHw->PLLControl12 = 0x38000700;
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pChipcHw->PLLControl22 = 0x00000015;
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/* Reset PLL2 */
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if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
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pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
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chipcHw_REG_PLL_CONFIG_A_RESET |
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chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
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chipcHw_REG_PLL_CONFIG_POWER_DOWN;
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} else {
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pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
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chipcHw_REG_PLL_CONFIG_A_RESET |
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chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
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chipcHw_REG_PLL_CONFIG_POWER_DOWN;
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}
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REG_LOCAL_IRQ_RESTORE;
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}
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/* Insert certain amount of delay before deasserting ARESET. */
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udelay(1);
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{
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REG_LOCAL_IRQ_SAVE;
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/* Remove analog reset and Power on the PLL */
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pChipcHw->PLLConfig2 &=
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~(chipcHw_REG_PLL_CONFIG_A_RESET |
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chipcHw_REG_PLL_CONFIG_POWER_DOWN);
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REG_LOCAL_IRQ_RESTORE;
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}
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/* Wait until PLL is locked */
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while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
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;
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{
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REG_LOCAL_IRQ_SAVE;
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/* Remove digital reset */
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pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
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REG_LOCAL_IRQ_RESTORE;
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}
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}
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EXPORT_SYMBOL(chipcHw_pll2Enable);
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/****************************************************************************/
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/**
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* @brief Initializes the PLL1
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*
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* This function initializes the PLL1
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*
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*/
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/****************************************************************************/
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void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
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{
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uint32_t pllPreDivider = 0;
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{
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REG_LOCAL_IRQ_SAVE;
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pChipcHw->PLLConfig =
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chipcHw_REG_PLL_CONFIG_D_RESET |
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chipcHw_REG_PLL_CONFIG_A_RESET;
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/* Setting VCO frequency */
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if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
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pllPreDivider =
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chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
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((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
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1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
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(chipcHw_REG_PLL_PREDIVIDER_P1 <<
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chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
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(chipcHw_REG_PLL_PREDIVIDER_P2 <<
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chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
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} else {
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pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
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chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
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(chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
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chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
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(chipcHw_REG_PLL_PREDIVIDER_P1 <<
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chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
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(chipcHw_REG_PLL_PREDIVIDER_P2 <<
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chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
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}
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/* Enable CHIPC registers to control the PLL */
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pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
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/* Set pre divider to get desired VCO frequency */
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pChipcHw->PLLPreDivider = pllPreDivider;
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/* Set NDIV Frac */
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if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
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pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
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chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
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} else {
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pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
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chipcHw_REG_PLL_DIVIDER_NDIV_f;
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}
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/* Reset PLL1 */
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if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
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pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
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chipcHw_REG_PLL_CONFIG_A_RESET |
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chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
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chipcHw_REG_PLL_CONFIG_POWER_DOWN;
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} else {
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pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
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chipcHw_REG_PLL_CONFIG_A_RESET |
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chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
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chipcHw_REG_PLL_CONFIG_POWER_DOWN;
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}
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REG_LOCAL_IRQ_RESTORE;
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/* Insert certain amount of delay before deasserting ARESET. */
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udelay(1);
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{
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REG_LOCAL_IRQ_SAVE;
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/* Remove analog reset and Power on the PLL */
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pChipcHw->PLLConfig &=
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~(chipcHw_REG_PLL_CONFIG_A_RESET |
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chipcHw_REG_PLL_CONFIG_POWER_DOWN);
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REG_LOCAL_IRQ_RESTORE;
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}
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/* Wait until PLL is locked */
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while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
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|| !(pChipcHw->
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PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
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;
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/* Remove digital reset */
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{
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REG_LOCAL_IRQ_SAVE;
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pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
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REG_LOCAL_IRQ_RESTORE;
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}
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}
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}
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EXPORT_SYMBOL(chipcHw_pll1Enable);
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/****************************************************************************/
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/**
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* @brief Initializes the chipc module
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*
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* This function initializes the PLLs and core system clocks
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*
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*/
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/****************************************************************************/
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void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */
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) {
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#if !(defined(__KERNEL__) && !defined(STANDALONE))
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delay_init();
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#endif
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/* Do not program PLL, when warm reset */
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if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
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chipcHw_pll1Enable(initParam->pllVcoFreqHz,
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initParam->ssSupport);
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chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
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} else {
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/* Clear sticky bits */
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chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
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}
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/* Clear sticky bits */
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chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
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/* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
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pChipcHw->ACLKClock =
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(pChipcHw->
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ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
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armBusRatio &
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chipcHw_REG_ACLKClock_CLK_DIV_MASK);
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/* Set various core component frequencies. The order in which this is done is important for some. */
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/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
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/* frequency to find its ratio with the BUS. Hence we must set the ARM first, followed by the BUS, */
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/* then VPM and RTBUS. */
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chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
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initParam->busClockFreqHz *
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initParam->armBusRatio);
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chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
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chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
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initParam->busClockFreqHz *
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initParam->vpmBusRatio);
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chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
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initParam->busClockFreqHz *
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initParam->ddrBusRatio);
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chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
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initParam->busClockFreqHz / 2);
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}
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