3e11e818bf
Intel Baytrail is based on Silvermont core so MSR_FSB_FREQ[2:0] == 0 means that the CPU reference clock runs at 83.3MHz. Add this missing frequency to the table. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Bin Gao <bin.gao@linux.intel.com> Cc: One Thousand Gnomes <gnomes@lxorguk.ukuu.org.uk> Cc: Ingo Molnar <mingo@kernel.org> Cc: H. Peter Anvin <hpa@zytor.com> Link: http://lkml.kernel.org/r/1392810750-18660-2-git-send-email-mika.westerberg@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
127 lines
3.4 KiB
C
127 lines
3.4 KiB
C
/*
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* tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms.
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*
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* TSC in Intel Atom SoC runs at a constant rate which can be figured
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* by this formula:
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* <maximum core-clock to bus-clock ratio> * <maximum resolved frequency>
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* See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5
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* for details.
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* Especially some Intel Atom SoCs don't have PIT(i8254) or HPET, so MSR
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* based calibration is the only option.
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*
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*
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* Copyright (C) 2013 Intel Corporation
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* Author: Bin Gao <bin.gao@intel.com>
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*
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* This file is released under the GPLv2.
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*/
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#include <linux/kernel.h>
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#include <asm/processor.h>
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#include <asm/setup.h>
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#include <asm/apic.h>
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#include <asm/param.h>
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/* CPU reference clock frequency: in KHz */
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#define FREQ_83 83200
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#define FREQ_100 99840
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#define FREQ_133 133200
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#define FREQ_166 166400
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#define MAX_NUM_FREQS 8
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/*
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* According to Intel 64 and IA-32 System Programming Guide,
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* if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
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* read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
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* Unfortunately some Intel Atom SoCs aren't quite compliant to this,
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* so we need manually differentiate SoC families. This is what the
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* field msr_plat does.
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*/
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struct freq_desc {
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u8 x86_family; /* CPU family */
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u8 x86_model; /* model */
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u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
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u32 freqs[MAX_NUM_FREQS];
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};
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static struct freq_desc freq_desc_tables[] = {
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/* PNW */
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{ 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
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/* CLV+ */
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{ 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
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/* TNG */
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{ 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
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/* VLV2 */
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{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
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/* ANN */
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{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
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};
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static int match_cpu(u8 family, u8 model)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
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if ((family == freq_desc_tables[i].x86_family) &&
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(model == freq_desc_tables[i].x86_model))
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return i;
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}
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return -1;
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}
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/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
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#define id_to_freq(cpu_index, freq_id) \
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(freq_desc_tables[cpu_index].freqs[freq_id])
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/*
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* Do MSR calibration only for known/supported CPUs.
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*
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* Returns the calibration value or 0 if MSR calibration failed.
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*/
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unsigned long try_msr_calibrate_tsc(void)
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{
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u32 lo, hi, ratio, freq_id, freq;
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unsigned long res;
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int cpu_index;
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cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
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if (cpu_index < 0)
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return 0;
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if (freq_desc_tables[cpu_index].msr_plat) {
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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ratio = (lo >> 8) & 0x1f;
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} else {
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rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
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ratio = (hi >> 8) & 0x1f;
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}
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pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
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if (!ratio)
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goto fail;
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/* Get FSB FREQ ID */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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freq_id = lo & 0x7;
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freq = id_to_freq(cpu_index, freq_id);
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pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
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freq_id, freq);
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if (!freq)
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goto fail;
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/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
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res = freq * ratio;
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pr_info("TSC runs at %lu KHz\n", res);
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#ifdef CONFIG_X86_LOCAL_APIC
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lapic_timer_frequency = (freq * 1000) / HZ;
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pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
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#endif
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return res;
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fail:
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pr_warn("Fast TSC calibration using MSR failed\n");
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return 0;
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}
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