0e1540208e
The PSS register reflects the power state of each island on SoC. It would be useful to know which of the islands is on or off at the momemnt. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Aubrey Li <aubrey.li@linux.intel.com> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Cc: Kumar P. Mahesh <mahesh.kumar.p@intel.com> Link: http://lkml.kernel.org/r/1421253575-22509-6-git-send-email-andriy.shevchenko@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
129 lines
3.8 KiB
C
129 lines
3.8 KiB
C
/*
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* Intel Atom SOC Power Management Controller Header File
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* Copyright (c) 2014, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#ifndef PMC_ATOM_H
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#define PMC_ATOM_H
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/* ValleyView Power Control Unit PCI Device ID */
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#define PCI_DEVICE_ID_VLV_PMC 0x0F1C
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/* PMC Memory mapped IO registers */
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#define PMC_BASE_ADDR_OFFSET 0x44
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#define PMC_BASE_ADDR_MASK 0xFFFFFE00
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#define PMC_MMIO_REG_LEN 0x100
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#define PMC_REG_BIT_WIDTH 32
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/* BIOS uses FUNC_DIS to disable specific function */
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#define PMC_FUNC_DIS 0x34
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#define PMC_FUNC_DIS_2 0x38
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/* S0ix wake event control */
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#define PMC_S0IX_WAKE_EN 0x3C
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#define BIT_LPC_CLOCK_RUN BIT(4)
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#define BIT_SHARED_IRQ_GPSC BIT(5)
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#define BIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
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#define BIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
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#define BIT_SHARED_IRQ_GPSS BIT(20)
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#define PMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \
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BIT_SHARED_IRQ_GPSC | \
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BIT_ORED_DEDICATED_IRQ_GPSS | \
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BIT_ORED_DEDICATED_IRQ_GPSC | \
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BIT_SHARED_IRQ_GPSS)
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/* The timers acumulate time spent in sleep state */
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#define PMC_S0IR_TMR 0x80
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#define PMC_S0I1_TMR 0x84
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#define PMC_S0I2_TMR 0x88
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#define PMC_S0I3_TMR 0x8C
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#define PMC_S0_TMR 0x90
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/* Sleep state counter is in units of of 32us */
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#define PMC_TMR_SHIFT 5
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/* Power status of power islands */
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#define PMC_PSS 0x98
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#define PMC_PSS_BIT_GBE BIT(0)
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#define PMC_PSS_BIT_SATA BIT(1)
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#define PMC_PSS_BIT_HDA BIT(2)
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#define PMC_PSS_BIT_SEC BIT(3)
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#define PMC_PSS_BIT_PCIE BIT(4)
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#define PMC_PSS_BIT_LPSS BIT(5)
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#define PMC_PSS_BIT_LPE BIT(6)
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#define PMC_PSS_BIT_DFX BIT(7)
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#define PMC_PSS_BIT_USH_CTRL BIT(8)
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#define PMC_PSS_BIT_USH_SUS BIT(9)
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#define PMC_PSS_BIT_USH_VCCS BIT(10)
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#define PMC_PSS_BIT_USH_VCCA BIT(11)
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#define PMC_PSS_BIT_OTG_CTRL BIT(12)
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#define PMC_PSS_BIT_OTG_VCCS BIT(13)
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#define PMC_PSS_BIT_OTG_VCCA_CLK BIT(14)
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#define PMC_PSS_BIT_OTG_VCCA BIT(15)
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#define PMC_PSS_BIT_USB BIT(16)
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#define PMC_PSS_BIT_USB_SUS BIT(17)
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/* These registers reflect D3 status of functions */
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#define PMC_D3_STS_0 0xA0
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#define BIT_LPSS1_F0_DMA BIT(0)
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#define BIT_LPSS1_F1_PWM1 BIT(1)
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#define BIT_LPSS1_F2_PWM2 BIT(2)
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#define BIT_LPSS1_F3_HSUART1 BIT(3)
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#define BIT_LPSS1_F4_HSUART2 BIT(4)
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#define BIT_LPSS1_F5_SPI BIT(5)
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#define BIT_LPSS1_F6_XXX BIT(6)
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#define BIT_LPSS1_F7_XXX BIT(7)
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#define BIT_SCC_EMMC BIT(8)
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#define BIT_SCC_SDIO BIT(9)
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#define BIT_SCC_SDCARD BIT(10)
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#define BIT_SCC_MIPI BIT(11)
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#define BIT_HDA BIT(12)
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#define BIT_LPE BIT(13)
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#define BIT_OTG BIT(14)
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#define BIT_USH BIT(15)
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#define BIT_GBE BIT(16)
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#define BIT_SATA BIT(17)
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#define BIT_USB_EHCI BIT(18)
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#define BIT_SEC BIT(19)
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#define BIT_PCIE_PORT0 BIT(20)
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#define BIT_PCIE_PORT1 BIT(21)
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#define BIT_PCIE_PORT2 BIT(22)
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#define BIT_PCIE_PORT3 BIT(23)
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#define BIT_LPSS2_F0_DMA BIT(24)
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#define BIT_LPSS2_F1_I2C1 BIT(25)
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#define BIT_LPSS2_F2_I2C2 BIT(26)
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#define BIT_LPSS2_F3_I2C3 BIT(27)
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#define BIT_LPSS2_F4_I2C4 BIT(28)
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#define BIT_LPSS2_F5_I2C5 BIT(29)
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#define BIT_LPSS2_F6_I2C6 BIT(30)
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#define BIT_LPSS2_F7_I2C7 BIT(31)
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#define PMC_D3_STS_1 0xA4
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#define BIT_SMB BIT(0)
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#define BIT_OTG_SS_PHY BIT(1)
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#define BIT_USH_SS_PHY BIT(2)
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#define BIT_DFX BIT(3)
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/* PMC I/O Registers */
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#define ACPI_BASE_ADDR_OFFSET 0x40
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#define ACPI_BASE_ADDR_MASK 0xFFFFFE00
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#define ACPI_MMIO_REG_LEN 0x100
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#define PM1_CNT 0x4
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#define SLEEP_TYPE_MASK 0xFFFFECFF
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#define SLEEP_TYPE_S5 0x1C00
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#define SLEEP_ENABLE 0x2000
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#endif /* PMC_ATOM_H */
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