7ef1def800
Added all the MBI units below and their associated read/write opcodes: - Host Bridge Arbiter - Host Bridge - Remote Management Unit - Memory Manager & eSRAM - SoC Unit Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com> Link: http://lkml.kernel.org/r/1399668248-24199-3-git-send-email-david.e.box@linux.intel.com Signed-off-by: David E. Box <david.e.box@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
145 lines
3.7 KiB
C
145 lines
3.7 KiB
C
/*
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* iosf_mbi.h: Intel OnChip System Fabric MailBox access support
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*/
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#ifndef IOSF_MBI_SYMS_H
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#define IOSF_MBI_SYMS_H
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#define MBI_MCR_OFFSET 0xD0
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#define MBI_MDR_OFFSET 0xD4
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#define MBI_MCRX_OFFSET 0xD8
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#define MBI_RD_MASK 0xFEFFFFFF
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#define MBI_WR_MASK 0X01000000
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#define MBI_MASK_HI 0xFFFFFF00
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#define MBI_MASK_LO 0x000000FF
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#define MBI_ENABLE 0xF0
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/* Baytrail available units */
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#define BT_MBI_UNIT_AUNIT 0x00
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#define BT_MBI_UNIT_SMC 0x01
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#define BT_MBI_UNIT_CPU 0x02
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#define BT_MBI_UNIT_BUNIT 0x03
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#define BT_MBI_UNIT_PMC 0x04
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#define BT_MBI_UNIT_GFX 0x06
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#define BT_MBI_UNIT_SMI 0x0C
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#define BT_MBI_UNIT_USB 0x43
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#define BT_MBI_UNIT_SATA 0xA3
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#define BT_MBI_UNIT_PCIE 0xA6
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/* Baytrail read/write opcodes */
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#define BT_MBI_AUNIT_READ 0x10
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#define BT_MBI_AUNIT_WRITE 0x11
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#define BT_MBI_SMC_READ 0x10
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#define BT_MBI_SMC_WRITE 0x11
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#define BT_MBI_CPU_READ 0x10
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#define BT_MBI_CPU_WRITE 0x11
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#define BT_MBI_BUNIT_READ 0x10
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#define BT_MBI_BUNIT_WRITE 0x11
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#define BT_MBI_PMC_READ 0x06
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#define BT_MBI_PMC_WRITE 0x07
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#define BT_MBI_GFX_READ 0x00
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#define BT_MBI_GFX_WRITE 0x01
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#define BT_MBI_SMIO_READ 0x06
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#define BT_MBI_SMIO_WRITE 0x07
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#define BT_MBI_USB_READ 0x06
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#define BT_MBI_USB_WRITE 0x07
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#define BT_MBI_SATA_READ 0x00
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#define BT_MBI_SATA_WRITE 0x01
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#define BT_MBI_PCIE_READ 0x00
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#define BT_MBI_PCIE_WRITE 0x01
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/* Quark available units */
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#define QRK_MBI_UNIT_HBA 0x00
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#define QRK_MBI_UNIT_HB 0x03
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#define QRK_MBI_UNIT_RMU 0x04
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#define QRK_MBI_UNIT_MM 0x05
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#define QRK_MBI_UNIT_MMESRAM 0x05
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#define QRK_MBI_UNIT_SOC 0x31
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/* Quark read/write opcodes */
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#define QRK_MBI_HBA_READ 0x10
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#define QRK_MBI_HBA_WRITE 0x11
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#define QRK_MBI_HB_READ 0x10
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#define QRK_MBI_HB_WRITE 0x11
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#define QRK_MBI_RMU_READ 0x10
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#define QRK_MBI_RMU_WRITE 0x11
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#define QRK_MBI_MM_READ 0x10
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#define QRK_MBI_MM_WRITE 0x11
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#define QRK_MBI_MMESRAM_READ 0x12
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#define QRK_MBI_MMESRAM_WRITE 0x13
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#define QRK_MBI_SOC_READ 0x06
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#define QRK_MBI_SOC_WRITE 0x07
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#if IS_ENABLED(CONFIG_IOSF_MBI)
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bool iosf_mbi_available(void);
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/**
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* iosf_mbi_read() - MailBox Interface read command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data to be read
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
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/**
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* iosf_mbi_write() - MailBox unmasked write command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data to be written
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
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/**
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* iosf_mbi_modify() - MailBox masked write command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data being modified
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* @mask: mask indicating bits in mdr to be modified
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
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#else /* CONFIG_IOSF_MBI is not enabled */
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static inline
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bool iosf_mbi_available(void)
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{
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return false;
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}
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static inline
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int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
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{
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WARN(1, "IOSF_MBI driver not available");
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return -EPERM;
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}
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static inline
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int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
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{
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WARN(1, "IOSF_MBI driver not available");
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return -EPERM;
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}
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static inline
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int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
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{
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WARN(1, "IOSF_MBI driver not available");
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return -EPERM;
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}
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#endif /* CONFIG_IOSF_MBI */
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#endif /* IOSF_MBI_SYMS_H */
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