bafe586583
Some platforms always enter the kernel in ARM mode even if the kernel is compiled for THUMB2. Add a small wrapper on top of secondary_startup() that switches into THUMB2 mode. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
712 lines
18 KiB
ArmAsm
712 lines
18 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Kernel startup code for all 32-bit CPUs
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/cp15.h>
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#include <asm/domain.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/pgtable.h>
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#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING)
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#include CONFIG_DEBUG_LL_INCLUDE
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#endif
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/*
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* swapper_pg_dir is the virtual address of the initial page table.
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* We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
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* make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
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* the least significant 16 bits to be 0x8000, but we could probably
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* relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
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*/
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#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
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#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
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#error KERNEL_RAM_VADDR must start at 0xXXXX8000
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#endif
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#ifdef CONFIG_ARM_LPAE
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/* LPAE requires an additional page for the PGD */
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#define PG_DIR_SIZE 0x5000
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#define PMD_ORDER 3
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#else
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#define PG_DIR_SIZE 0x4000
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#define PMD_ORDER 2
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
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.macro pgtbl, rd, phys
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add \rd, \phys, #TEXT_OFFSET
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sub \rd, \rd, #PG_DIR_SIZE
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.endm
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* This is normally called from the decompressor code. The requirements
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* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
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* r1 = machine nr, r2 = atags or dtb pointer.
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*
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* This code is mostly position independent, so if you link the kernel at
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* 0xc0008000, you call this at __pa(0xc0008000).
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*
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* See linux/arch/arm/tools/mach-types for the complete list of machine
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* numbers for r1.
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*
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* We're trying to keep crap to a minimum; DO NOT add any machine specific
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* crap here - that's what the boot loader (or in extreme, well justified
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* circumstances, zImage) is for.
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*/
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.arm
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__HEAD
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ENTRY(stext)
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ARM_BE8(setend be ) @ ensure we are in BE8 mode
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THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
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THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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THUMB( .thumb ) @ switch to Thumb now.
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THUMB(1: )
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#ifdef CONFIG_ARM_VIRT_EXT
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bl __hyp_stub_install
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#endif
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@ ensure svc mode and all interrupts masked
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safe_svcmode_maskall r9
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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THUMB( it eq ) @ force fixup-able long branch encoding
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beq __error_p @ yes, error 'p'
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#ifdef CONFIG_ARM_LPAE
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mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
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and r3, r3, #0xf @ extract VMSA support
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cmp r3, #5 @ long-descriptor translation table format?
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THUMB( it lo ) @ force fixup-able long branch encoding
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blo __error_lpae @ only classic page table format
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#endif
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#ifndef CONFIG_XIP_KERNEL
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adr r3, 2f
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ldmia r3, {r4, r8}
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sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
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add r8, r8, r4 @ PHYS_OFFSET
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#else
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ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case
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#endif
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/*
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* r1 = machine no, r2 = atags or dtb,
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* r8 = phys_offset, r9 = cpuid, r10 = procinfo
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*/
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bl __vet_atags
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#ifdef CONFIG_SMP_ON_UP
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bl __fixup_smp
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#endif
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
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bl __fixup_pv_table
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#endif
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bl __create_page_tables
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/*
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* The following calls CPU specific code in a position independent
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* manner. See arch/arm/mm/proc-*.S for details. r10 = base of
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* xxx_proc_info structure selected by __lookup_processor_type
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* above. On return, the CPU will be ready for the MMU to be
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* turned on, and r0 will hold the CPU control register value.
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*/
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ldr r13, =__mmap_switched @ address to jump to after
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@ mmu has been enabled
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adr lr, BSYM(1f) @ return (PIC) address
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mov r8, r4 @ set TTBR1 to swapper_pg_dir
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ARM( add pc, r10, #PROCINFO_INITFUNC )
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THUMB( add r12, r10, #PROCINFO_INITFUNC )
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THUMB( ret r12 )
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1: b __enable_mmu
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ENDPROC(stext)
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.ltorg
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#ifndef CONFIG_XIP_KERNEL
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2: .long .
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.long PAGE_OFFSET
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#endif
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/*
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* Setup the initial page tables. We only setup the barest
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* amount which are required to get the kernel running, which
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* generally means mapping in the kernel code.
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*
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* r8 = phys_offset, r9 = cpuid, r10 = procinfo
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*
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* Returns:
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* r0, r3, r5-r7 corrupted
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* r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
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*/
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__create_page_tables:
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pgtbl r4, r8 @ page table address
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/*
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* Clear the swapper page table
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*/
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mov r0, r4
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mov r3, #0
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add r6, r0, #PG_DIR_SIZE
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1: str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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teq r0, r6
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bne 1b
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#ifdef CONFIG_ARM_LPAE
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/*
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* Build the PGD table (first level) to point to the PMD table. A PGD
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* entry is 64-bit wide.
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*/
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mov r0, r4
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add r3, r4, #0x1000 @ first PMD table address
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orr r3, r3, #3 @ PGD block type
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mov r6, #4 @ PTRS_PER_PGD
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mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER
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1:
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#ifdef CONFIG_CPU_ENDIAN_BE8
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str r7, [r0], #4 @ set top PGD entry bits
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str r3, [r0], #4 @ set bottom PGD entry bits
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#else
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str r3, [r0], #4 @ set bottom PGD entry bits
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str r7, [r0], #4 @ set top PGD entry bits
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#endif
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add r3, r3, #0x1000 @ next PMD table
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subs r6, r6, #1
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bne 1b
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add r4, r4, #0x1000 @ point to the PMD tables
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#ifdef CONFIG_CPU_ENDIAN_BE8
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add r4, r4, #4 @ we only write the bottom word
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#endif
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#endif
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ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
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/*
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* Create identity mapping to cater for __enable_mmu.
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* This identity mapping will be removed by paging_init().
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*/
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adr r0, __turn_mmu_on_loc
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ldmia r0, {r3, r5, r6}
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sub r0, r0, r3 @ virt->phys offset
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add r5, r5, r0 @ phys __turn_mmu_on
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add r6, r6, r0 @ phys __turn_mmu_on_end
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mov r5, r5, lsr #SECTION_SHIFT
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mov r6, r6, lsr #SECTION_SHIFT
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1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
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str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
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cmp r5, r6
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addlo r5, r5, #1 @ next section
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blo 1b
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/*
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* Map our RAM from the start to the end of the kernel .bss section.
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*/
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add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
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ldr r6, =(_end - 1)
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orr r3, r8, r7
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add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
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1: str r3, [r0], #1 << PMD_ORDER
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add r3, r3, #1 << SECTION_SHIFT
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cmp r0, r6
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bls 1b
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#ifdef CONFIG_XIP_KERNEL
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/*
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* Map the kernel image separately as it is not located in RAM.
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*/
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#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
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mov r3, pc
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mov r3, r3, lsr #SECTION_SHIFT
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orr r3, r7, r3, lsl #SECTION_SHIFT
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add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
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str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
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ldr r6, =(_edata_loc - 1)
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add r0, r0, #1 << PMD_ORDER
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add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
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1: cmp r0, r6
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add r3, r3, #1 << SECTION_SHIFT
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strls r3, [r0], #1 << PMD_ORDER
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bls 1b
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#endif
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/*
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* Then map boot params address in r2 if specified.
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* We map 2 sections in case the ATAGs/DTB crosses a section boundary.
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*/
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mov r0, r2, lsr #SECTION_SHIFT
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movs r0, r0, lsl #SECTION_SHIFT
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subne r3, r0, r8
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addne r3, r3, #PAGE_OFFSET
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addne r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
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orrne r6, r7, r0
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strne r6, [r3], #1 << PMD_ORDER
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addne r6, r6, #1 << SECTION_SHIFT
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strne r6, [r3]
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#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8)
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sub r4, r4, #4 @ Fixup page table pointer
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@ for 64-bit descriptors
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#endif
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#ifdef CONFIG_DEBUG_LL
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#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
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/*
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* Map in IO space for serial debugging.
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* This allows debug messages to be output
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* via a serial console before paging_init.
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*/
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addruart r7, r3, r0
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mov r3, r3, lsr #SECTION_SHIFT
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mov r3, r3, lsl #PMD_ORDER
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add r0, r4, r3
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mov r3, r7, lsr #SECTION_SHIFT
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ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
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orr r3, r7, r3, lsl #SECTION_SHIFT
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#ifdef CONFIG_ARM_LPAE
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mov r7, #1 << (54 - 32) @ XN
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#ifdef CONFIG_CPU_ENDIAN_BE8
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str r7, [r0], #4
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str r3, [r0], #4
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#else
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str r3, [r0], #4
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str r7, [r0], #4
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#endif
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#else
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orr r3, r3, #PMD_SECT_XN
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str r3, [r0], #4
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#endif
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#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
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/* we don't need any serial debugging mappings */
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ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
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#endif
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#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
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/*
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* If we're using the NetWinder or CATS, we also need to map
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* in the 16550-type serial port for the debug messages
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*/
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add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
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orr r3, r7, #0x7c000000
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str r3, [r0]
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#endif
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#ifdef CONFIG_ARCH_RPC
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/*
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* Map in screen at 0x02000000 & SCREEN2_BASE
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* Similar reasons here - for debug. This is
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* only for Acorn RiscPC architectures.
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*/
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add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
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orr r3, r7, #0x02000000
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str r3, [r0]
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add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
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str r3, [r0]
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#endif
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#endif
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#ifdef CONFIG_ARM_LPAE
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sub r4, r4, #0x1000 @ point to the PGD table
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mov r4, r4, lsr #ARCH_PGD_SHIFT
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#endif
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ret lr
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ENDPROC(__create_page_tables)
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.ltorg
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.align
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__turn_mmu_on_loc:
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.long .
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.long __turn_mmu_on
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.long __turn_mmu_on_end
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#if defined(CONFIG_SMP)
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.text
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ENTRY(secondary_startup_arm)
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.arm
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THUMB( adr r9, BSYM(1f) ) @ Kernel is entered in ARM.
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THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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THUMB( .thumb ) @ switch to Thumb now.
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THUMB(1: )
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*
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* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
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* the processor type - there is no need to check the machine type
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* as it has already been validated by the primary processor.
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*/
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ARM_BE8(setend be) @ ensure we are in BE8 mode
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#ifdef CONFIG_ARM_VIRT_EXT
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bl __hyp_stub_install_secondary
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#endif
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safe_svcmode_maskall r9
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type
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movs r10, r5 @ invalid processor?
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moveq r0, #'p' @ yes, error 'p'
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THUMB( it eq ) @ force fixup-able long branch encoding
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beq __error_p
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/*
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* Use the page tables supplied from __cpu_up.
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*/
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adr r4, __secondary_data
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ldmia r4, {r5, r7, r12} @ address to jump to after
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sub lr, r4, r5 @ mmu has been enabled
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ldr r4, [r7, lr] @ get secondary_data.pgdir
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add r7, r7, #4
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ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
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adr lr, BSYM(__enable_mmu) @ return address
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mov r13, r12 @ __secondary_switched address
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ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
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@ (return control reg)
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THUMB( add r12, r10, #PROCINFO_INITFUNC )
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THUMB( ret r12 )
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ENDPROC(secondary_startup)
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ENDPROC(secondary_startup_arm)
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/*
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* r6 = &secondary_data
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*/
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ENTRY(__secondary_switched)
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ldr sp, [r7, #4] @ get secondary_data.stack
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mov fp, #0
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b secondary_start_kernel
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ENDPROC(__secondary_switched)
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.align
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.type __secondary_data, %object
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__secondary_data:
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.long .
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.long secondary_data
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.long __secondary_switched
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#endif /* defined(CONFIG_SMP) */
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/*
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* Setup common bits before finally enabling the MMU. Essentially
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* this is just loading the page table pointer and domain access
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* registers.
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*
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* r0 = cp#15 control register
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* r1 = machine ID
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* r2 = atags or dtb pointer
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* r4 = page table (see ARCH_PGD_SHIFT in asm/memory.h)
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* r9 = processor ID
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* r13 = *virtual* address to jump to upon completion
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*/
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__enable_mmu:
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#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6
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orr r0, r0, #CR_A
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#else
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bic r0, r0, #CR_A
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#endif
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CR_C
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#endif
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#ifdef CONFIG_CPU_BPREDICT_DISABLE
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bic r0, r0, #CR_Z
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #CR_I
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#endif
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#ifndef CONFIG_ARM_LPAE
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mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_IO, DOMAIN_CLIENT))
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mcr p15, 0, r5, c3, c0, 0 @ load domain access register
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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#endif
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b __turn_mmu_on
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ENDPROC(__enable_mmu)
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/*
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* Enable the MMU. This completely changes the structure of the visible
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* memory space. You will not be able to trace execution through this.
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* If you have an enquiry about this, *please* check the linux-arm-kernel
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* mailing list archives BEFORE sending another post to the list.
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*
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* r0 = cp#15 control register
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* r1 = machine ID
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* r2 = atags or dtb pointer
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* r9 = processor ID
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* r13 = *virtual* address to jump to upon completion
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*
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* other registers depend on the function called upon completion
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*/
|
|
.align 5
|
|
.pushsection .idmap.text, "ax"
|
|
ENTRY(__turn_mmu_on)
|
|
mov r0, r0
|
|
instr_sync
|
|
mcr p15, 0, r0, c1, c0, 0 @ write control reg
|
|
mrc p15, 0, r3, c0, c0, 0 @ read id reg
|
|
instr_sync
|
|
mov r3, r3
|
|
mov r3, r13
|
|
ret r3
|
|
__turn_mmu_on_end:
|
|
ENDPROC(__turn_mmu_on)
|
|
.popsection
|
|
|
|
|
|
#ifdef CONFIG_SMP_ON_UP
|
|
__HEAD
|
|
__fixup_smp:
|
|
and r3, r9, #0x000f0000 @ architecture version
|
|
teq r3, #0x000f0000 @ CPU ID supported?
|
|
bne __fixup_smp_on_up @ no, assume UP
|
|
|
|
bic r3, r9, #0x00ff0000
|
|
bic r3, r3, #0x0000000f @ mask 0xff00fff0
|
|
mov r4, #0x41000000
|
|
orr r4, r4, #0x0000b000
|
|
orr r4, r4, #0x00000020 @ val 0x4100b020
|
|
teq r3, r4 @ ARM 11MPCore?
|
|
reteq lr @ yes, assume SMP
|
|
|
|
mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
|
|
and r0, r0, #0xc0000000 @ multiprocessing extensions and
|
|
teq r0, #0x80000000 @ not part of a uniprocessor system?
|
|
bne __fixup_smp_on_up @ no, assume UP
|
|
|
|
@ Core indicates it is SMP. Check for Aegis SOC where a single
|
|
@ Cortex-A9 CPU is present but SMP operations fault.
|
|
mov r4, #0x41000000
|
|
orr r4, r4, #0x0000c000
|
|
orr r4, r4, #0x00000090
|
|
teq r3, r4 @ Check for ARM Cortex-A9
|
|
retne lr @ Not ARM Cortex-A9,
|
|
|
|
@ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the
|
|
@ below address check will need to be #ifdef'd or equivalent
|
|
@ for the Aegis platform.
|
|
mrc p15, 4, r0, c15, c0 @ get SCU base address
|
|
teq r0, #0x0 @ '0' on actual UP A9 hardware
|
|
beq __fixup_smp_on_up @ So its an A9 UP
|
|
ldr r0, [r0, #4] @ read SCU Config
|
|
ARM_BE8(rev r0, r0) @ byteswap if big endian
|
|
and r0, r0, #0x3 @ number of CPUs
|
|
teq r0, #0x0 @ is 1?
|
|
retne lr
|
|
|
|
__fixup_smp_on_up:
|
|
adr r0, 1f
|
|
ldmia r0, {r3 - r5}
|
|
sub r3, r0, r3
|
|
add r4, r4, r3
|
|
add r5, r5, r3
|
|
b __do_fixup_smp_on_up
|
|
ENDPROC(__fixup_smp)
|
|
|
|
.align
|
|
1: .word .
|
|
.word __smpalt_begin
|
|
.word __smpalt_end
|
|
|
|
.pushsection .data
|
|
.globl smp_on_up
|
|
smp_on_up:
|
|
ALT_SMP(.long 1)
|
|
ALT_UP(.long 0)
|
|
.popsection
|
|
#endif
|
|
|
|
.text
|
|
__do_fixup_smp_on_up:
|
|
cmp r4, r5
|
|
reths lr
|
|
ldmia r4!, {r0, r6}
|
|
ARM( str r6, [r0, r3] )
|
|
THUMB( add r0, r0, r3 )
|
|
#ifdef __ARMEB__
|
|
THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
|
|
#endif
|
|
THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
|
|
THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
|
|
THUMB( strh r6, [r0] )
|
|
b __do_fixup_smp_on_up
|
|
ENDPROC(__do_fixup_smp_on_up)
|
|
|
|
ENTRY(fixup_smp)
|
|
stmfd sp!, {r4 - r6, lr}
|
|
mov r4, r0
|
|
add r5, r0, r1
|
|
mov r3, #0
|
|
bl __do_fixup_smp_on_up
|
|
ldmfd sp!, {r4 - r6, pc}
|
|
ENDPROC(fixup_smp)
|
|
|
|
#ifdef __ARMEB__
|
|
#define LOW_OFFSET 0x4
|
|
#define HIGH_OFFSET 0x0
|
|
#else
|
|
#define LOW_OFFSET 0x0
|
|
#define HIGH_OFFSET 0x4
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
|
|
|
|
/* __fixup_pv_table - patch the stub instructions with the delta between
|
|
* PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
|
|
* can be expressed by an immediate shifter operand. The stub instruction
|
|
* has a form of '(add|sub) rd, rn, #imm'.
|
|
*/
|
|
__HEAD
|
|
__fixup_pv_table:
|
|
adr r0, 1f
|
|
ldmia r0, {r3-r7}
|
|
mvn ip, #0
|
|
subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
|
|
add r4, r4, r3 @ adjust table start address
|
|
add r5, r5, r3 @ adjust table end address
|
|
add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
|
|
add r7, r7, r3 @ adjust __pv_offset address
|
|
mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN
|
|
str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
|
|
strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
|
|
mov r6, r3, lsr #24 @ constant for add/sub instructions
|
|
teq r3, r6, lsl #24 @ must be 16MiB aligned
|
|
THUMB( it ne @ cross section branch )
|
|
bne __error
|
|
str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits
|
|
b __fixup_a_pv_table
|
|
ENDPROC(__fixup_pv_table)
|
|
|
|
.align
|
|
1: .long .
|
|
.long __pv_table_begin
|
|
.long __pv_table_end
|
|
2: .long __pv_phys_pfn_offset
|
|
.long __pv_offset
|
|
|
|
.text
|
|
__fixup_a_pv_table:
|
|
adr r0, 3f
|
|
ldr r6, [r0]
|
|
add r6, r6, r3
|
|
ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
|
|
ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
|
|
mov r6, r6, lsr #24
|
|
cmn r0, #1
|
|
#ifdef CONFIG_THUMB2_KERNEL
|
|
moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
|
|
lsls r6, #24
|
|
beq 2f
|
|
clz r7, r6
|
|
lsr r6, #24
|
|
lsl r6, r7
|
|
bic r6, #0x0080
|
|
lsrs r7, #1
|
|
orrcs r6, #0x0080
|
|
orr r6, r6, r7, lsl #12
|
|
orr r6, #0x4000
|
|
b 2f
|
|
1: add r7, r3
|
|
ldrh ip, [r7, #2]
|
|
ARM_BE8(rev16 ip, ip)
|
|
tst ip, #0x4000
|
|
and ip, #0x8f00
|
|
orrne ip, r6 @ mask in offset bits 31-24
|
|
orreq ip, r0 @ mask in offset bits 7-0
|
|
ARM_BE8(rev16 ip, ip)
|
|
strh ip, [r7, #2]
|
|
bne 2f
|
|
ldrh ip, [r7]
|
|
ARM_BE8(rev16 ip, ip)
|
|
bic ip, #0x20
|
|
orr ip, ip, r0, lsr #16
|
|
ARM_BE8(rev16 ip, ip)
|
|
strh ip, [r7]
|
|
2: cmp r4, r5
|
|
ldrcc r7, [r4], #4 @ use branch for delay slot
|
|
bcc 1b
|
|
bx lr
|
|
#else
|
|
#ifdef CONFIG_CPU_ENDIAN_BE8
|
|
moveq r0, #0x00004000 @ set bit 22, mov to mvn instruction
|
|
#else
|
|
moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
|
|
#endif
|
|
b 2f
|
|
1: ldr ip, [r7, r3]
|
|
#ifdef CONFIG_CPU_ENDIAN_BE8
|
|
@ in BE8, we load data in BE, but instructions still in LE
|
|
bic ip, ip, #0xff000000
|
|
tst ip, #0x000f0000 @ check the rotation field
|
|
orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
|
|
biceq ip, ip, #0x00004000 @ clear bit 22
|
|
orreq ip, ip, r0 @ mask in offset bits 7-0
|
|
#else
|
|
bic ip, ip, #0x000000ff
|
|
tst ip, #0xf00 @ check the rotation field
|
|
orrne ip, ip, r6 @ mask in offset bits 31-24
|
|
biceq ip, ip, #0x400000 @ clear bit 22
|
|
orreq ip, ip, r0 @ mask in offset bits 7-0
|
|
#endif
|
|
str ip, [r7, r3]
|
|
2: cmp r4, r5
|
|
ldrcc r7, [r4], #4 @ use branch for delay slot
|
|
bcc 1b
|
|
ret lr
|
|
#endif
|
|
ENDPROC(__fixup_a_pv_table)
|
|
|
|
.align
|
|
3: .long __pv_offset
|
|
|
|
ENTRY(fixup_pv_table)
|
|
stmfd sp!, {r4 - r7, lr}
|
|
mov r3, #0 @ no offset
|
|
mov r4, r0 @ r0 = table start
|
|
add r5, r0, r1 @ r1 = table size
|
|
bl __fixup_a_pv_table
|
|
ldmfd sp!, {r4 - r7, pc}
|
|
ENDPROC(fixup_pv_table)
|
|
|
|
.data
|
|
.globl __pv_phys_pfn_offset
|
|
.type __pv_phys_pfn_offset, %object
|
|
__pv_phys_pfn_offset:
|
|
.word 0
|
|
.size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset
|
|
|
|
.globl __pv_offset
|
|
.type __pv_offset, %object
|
|
__pv_offset:
|
|
.quad 0
|
|
.size __pv_offset, . -__pv_offset
|
|
#endif
|
|
|
|
#include "head-common.S"
|