 0d00c488f3
			
		
	
	
	0d00c488f3
	
	
	
		
			
			With dma compliance / IOMMU support added to the driver in kernel 3.13, the dma addresses can exceed 44 bits, which is what we support in 32-bit mode and with GMR1. So in 32-bit mode and optionally in 64-bit mode, restrict the dma addresses to 44 bits, and strip the old GMR1 code. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Reviewed-by: Jakob Bornecrantz <jakob@vmware.com> Cc: stable@vger.kernel.org
		
			
				
	
	
		
			151 lines
		
	
	
	
		
			4.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			151 lines
		
	
	
	
		
			4.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /**************************************************************************
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|  *
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|  * Copyright © 2009-2011 VMware, Inc., Palo Alto, CA., USA
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|  * All Rights Reserved.
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a
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|  * copy of this software and associated documentation files (the
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|  * "Software"), to deal in the Software without restriction, including
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|  * without limitation the rights to use, copy, modify, merge, publish,
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|  * distribute, sub license, and/or sell copies of the Software, and to
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|  * permit persons to whom the Software is furnished to do so, subject to
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|  * the following conditions:
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|  *
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|  * The above copyright notice and this permission notice (including the
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|  * next paragraph) shall be included in all copies or substantial portions
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|  * of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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|  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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|  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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|  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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|  * USE OR OTHER DEALINGS IN THE SOFTWARE.
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|  *
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|  **************************************************************************/
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| 
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| #include "vmwgfx_drv.h"
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| #include <drm/drmP.h>
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| #include <drm/ttm/ttm_bo_driver.h>
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| 
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| #define VMW_PPN_SIZE (sizeof(unsigned long))
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| /* A future safe maximum remap size. */
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| #define VMW_PPN_PER_REMAP ((31 * 1024) / VMW_PPN_SIZE)
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| #define DMA_ADDR_INVALID ((dma_addr_t) 0)
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| #define DMA_PAGE_INVALID 0UL
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| 
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| static int vmw_gmr2_bind(struct vmw_private *dev_priv,
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| 			 struct vmw_piter *iter,
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| 			 unsigned long num_pages,
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| 			 int gmr_id)
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| {
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| 	SVGAFifoCmdDefineGMR2 define_cmd;
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| 	SVGAFifoCmdRemapGMR2 remap_cmd;
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| 	uint32_t *cmd;
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| 	uint32_t *cmd_orig;
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| 	uint32_t define_size = sizeof(define_cmd) + sizeof(*cmd);
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| 	uint32_t remap_num = num_pages / VMW_PPN_PER_REMAP + ((num_pages % VMW_PPN_PER_REMAP) > 0);
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| 	uint32_t remap_size = VMW_PPN_SIZE * num_pages + (sizeof(remap_cmd) + sizeof(*cmd)) * remap_num;
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| 	uint32_t remap_pos = 0;
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| 	uint32_t cmd_size = define_size + remap_size;
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| 	uint32_t i;
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| 
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| 	cmd_orig = cmd = vmw_fifo_reserve(dev_priv, cmd_size);
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| 	if (unlikely(cmd == NULL))
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| 		return -ENOMEM;
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| 
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| 	define_cmd.gmrId = gmr_id;
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| 	define_cmd.numPages = num_pages;
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| 
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| 	*cmd++ = SVGA_CMD_DEFINE_GMR2;
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| 	memcpy(cmd, &define_cmd, sizeof(define_cmd));
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| 	cmd += sizeof(define_cmd) / sizeof(*cmd);
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| 
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| 	/*
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| 	 * Need to split the command if there are too many
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| 	 * pages that goes into the gmr.
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| 	 */
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| 
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| 	remap_cmd.gmrId = gmr_id;
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| 	remap_cmd.flags = (VMW_PPN_SIZE > sizeof(*cmd)) ?
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| 		SVGA_REMAP_GMR2_PPN64 : SVGA_REMAP_GMR2_PPN32;
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| 
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| 	while (num_pages > 0) {
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| 		unsigned long nr = min(num_pages, (unsigned long)VMW_PPN_PER_REMAP);
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| 
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| 		remap_cmd.offsetPages = remap_pos;
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| 		remap_cmd.numPages = nr;
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| 
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| 		*cmd++ = SVGA_CMD_REMAP_GMR2;
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| 		memcpy(cmd, &remap_cmd, sizeof(remap_cmd));
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| 		cmd += sizeof(remap_cmd) / sizeof(*cmd);
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| 
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| 		for (i = 0; i < nr; ++i) {
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| 			if (VMW_PPN_SIZE <= 4)
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| 				*cmd = vmw_piter_dma_addr(iter) >> PAGE_SHIFT;
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| 			else
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| 				*((uint64_t *)cmd) = vmw_piter_dma_addr(iter) >>
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| 					PAGE_SHIFT;
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| 
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| 			cmd += VMW_PPN_SIZE / sizeof(*cmd);
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| 			vmw_piter_next(iter);
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| 		}
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| 
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| 		num_pages -= nr;
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| 		remap_pos += nr;
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| 	}
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| 
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| 	BUG_ON(cmd != cmd_orig + cmd_size / sizeof(*cmd));
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| 
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| 	vmw_fifo_commit(dev_priv, cmd_size);
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| 
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| 	return 0;
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| }
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| 
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| static void vmw_gmr2_unbind(struct vmw_private *dev_priv,
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| 			    int gmr_id)
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| {
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| 	SVGAFifoCmdDefineGMR2 define_cmd;
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| 	uint32_t define_size = sizeof(define_cmd) + 4;
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| 	uint32_t *cmd;
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| 
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| 	cmd = vmw_fifo_reserve(dev_priv, define_size);
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| 	if (unlikely(cmd == NULL)) {
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| 		DRM_ERROR("GMR2 unbind failed.\n");
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| 		return;
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| 	}
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| 	define_cmd.gmrId = gmr_id;
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| 	define_cmd.numPages = 0;
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| 
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| 	*cmd++ = SVGA_CMD_DEFINE_GMR2;
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| 	memcpy(cmd, &define_cmd, sizeof(define_cmd));
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| 
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| 	vmw_fifo_commit(dev_priv, define_size);
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| }
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| 
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| 
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| int vmw_gmr_bind(struct vmw_private *dev_priv,
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| 		 const struct vmw_sg_table *vsgt,
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| 		 unsigned long num_pages,
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| 		 int gmr_id)
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| {
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| 	struct vmw_piter data_iter;
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| 
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| 	vmw_piter_start(&data_iter, vsgt, 0);
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| 
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| 	if (unlikely(!vmw_piter_next(&data_iter)))
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| 		return 0;
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| 
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| 	if (unlikely(!(dev_priv->capabilities & SVGA_CAP_GMR2)))
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| 		return -EINVAL;
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| 
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| 	return vmw_gmr2_bind(dev_priv, &data_iter, num_pages, gmr_id);
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| }
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| 
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| 
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| void vmw_gmr_unbind(struct vmw_private *dev_priv, int gmr_id)
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| {
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| 	if (likely(dev_priv->capabilities & SVGA_CAP_GMR2))
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| 		vmw_gmr2_unbind(dev_priv, gmr_id);
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| }
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