09f75cd7bf
We now have struct net_device_stats embedded in struct net_device, and the default ->get_stats() hook does the obvious thing for us. Run through drivers/net/* and remove the driver-local storage of statistics, and driver-local ->get_stats() hook where applicable. This was just the low-hanging fruit in drivers/net; plenty more drivers remain to be updated. [ Resolved conflicts with napi_struct changes and fix sunqe build regression... -DaveM ] Signed-off-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: David S. Miller <davem@davemloft.net>
254 lines
10 KiB
C
254 lines
10 KiB
C
/*
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* 7990.h -- LANCE ethernet IC generic routines.
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* This is an attempt to separate out the bits of various ethernet
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* drivers that are common because they all use the AMD 7990 LANCE
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* (Local Area Network Controller for Ethernet) chip.
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*
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* Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
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*
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* Most of this stuff was obtained by looking at other LANCE drivers,
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* in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
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*/
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#ifndef _7990_H
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#define _7990_H
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/* The lance only has two register locations. We communicate mostly via memory. */
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#define LANCE_RDP 0 /* Register Data Port */
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#define LANCE_RAP 2 /* Register Address Port */
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/* Transmit/receive ring definitions.
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* We allow the specific drivers to override these defaults if they want to.
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* NB: according to lance.c, increasing the number of buffers is a waste
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* of space and reduces the chance that an upper layer will be able to
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* reorder queued Tx packets based on priority. [Clearly there is a minimum
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* limit too: too small and we drop rx packets and can't tx at full speed.]
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* 4+4 seems to be the usual setting; the atarilance driver uses 3 and 5.
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*/
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/* Blast! This won't work. The problem is that we can't specify a default
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* setting because that would cause the lance_init_block struct to be
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* too long (and overflow the RAM on shared-memory cards like the HP LANCE.
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*/
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#ifndef LANCE_LOG_TX_BUFFERS
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#define LANCE_LOG_TX_BUFFERS 1
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#define LANCE_LOG_RX_BUFFERS 3
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#endif
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#define TX_RING_SIZE (1<<LANCE_LOG_TX_BUFFERS)
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#define RX_RING_SIZE (1<<LANCE_LOG_RX_BUFFERS)
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#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
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#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
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#define TX_RING_LEN_BITS ((LANCE_LOG_TX_BUFFERS) << 29)
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#define RX_RING_LEN_BITS ((LANCE_LOG_RX_BUFFERS) << 29)
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#define PKT_BUFF_SIZE (1544)
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#define RX_BUFF_SIZE PKT_BUFF_SIZE
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#define TX_BUFF_SIZE PKT_BUFF_SIZE
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/* Each receive buffer is described by a receive message descriptor (RMD) */
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struct lance_rx_desc {
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volatile unsigned short rmd0; /* low address of packet */
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volatile unsigned char rmd1_bits; /* descriptor bits */
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volatile unsigned char rmd1_hadr; /* high address of packet */
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volatile short length; /* This length is 2s complement (negative)!
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* Buffer length
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*/
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volatile unsigned short mblength; /* Actual number of bytes received */
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};
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/* Ditto for TMD: */
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struct lance_tx_desc {
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volatile unsigned short tmd0; /* low address of packet */
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volatile unsigned char tmd1_bits; /* descriptor bits */
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volatile unsigned char tmd1_hadr; /* high address of packet */
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volatile short length; /* Length is 2s complement (negative)! */
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volatile unsigned short misc;
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};
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/* There are three memory structures accessed by the LANCE:
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* the initialization block, the receive and transmit descriptor rings,
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* and the data buffers themselves. In fact we might as well put the
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* init block,the Tx and Rx rings and the buffers together in memory:
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*/
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struct lance_init_block {
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volatile unsigned short mode; /* Pre-set mode (reg. 15) */
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volatile unsigned char phys_addr[6]; /* Physical ethernet address */
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volatile unsigned filter[2]; /* Multicast filter (64 bits) */
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/* Receive and transmit ring base, along with extra bits. */
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volatile unsigned short rx_ptr; /* receive descriptor addr */
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volatile unsigned short rx_len; /* receive len and high addr */
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volatile unsigned short tx_ptr; /* transmit descriptor addr */
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volatile unsigned short tx_len; /* transmit len and high addr */
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/* The Tx and Rx ring entries must be aligned on 8-byte boundaries.
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* This will be true if this whole struct is 8-byte aligned.
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*/
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volatile struct lance_tx_desc btx_ring[TX_RING_SIZE];
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volatile struct lance_rx_desc brx_ring[RX_RING_SIZE];
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volatile char tx_buf [TX_RING_SIZE][TX_BUFF_SIZE];
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volatile char rx_buf [RX_RING_SIZE][RX_BUFF_SIZE];
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/* we use this just to make the struct big enough that we can move its startaddr
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* in order to force alignment to an eight byte boundary.
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*/
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};
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/* This is where we keep all the stuff the driver needs to know about.
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* I'm definitely unhappy about the mechanism for allowing specific
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* drivers to add things...
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*/
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struct lance_private
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{
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char *name;
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unsigned long base;
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volatile struct lance_init_block *init_block; /* CPU address of RAM */
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volatile struct lance_init_block *lance_init_block; /* LANCE address of RAM */
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int rx_new, tx_new;
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int rx_old, tx_old;
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int lance_log_rx_bufs, lance_log_tx_bufs;
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int rx_ring_mod_mask, tx_ring_mod_mask;
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int tpe; /* TPE is selected */
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int auto_select; /* cable-selection is by carrier */
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unsigned short busmaster_regval;
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unsigned int irq; /* IRQ to register */
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/* This is because the HP LANCE is disgusting and you have to check
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* a DIO-specific register every time you read/write the LANCE regs :-<
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* [could we get away with making these some sort of macro?]
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*/
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void (*writerap)(void *, unsigned short);
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void (*writerdp)(void *, unsigned short);
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unsigned short (*readrdp)(void *);
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spinlock_t devlock;
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char tx_full;
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};
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/*
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* Am7990 Control and Status Registers
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*/
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#define LE_CSR0 0x0000 /* LANCE Controller Status */
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#define LE_CSR1 0x0001 /* IADR[15:0] (bit0==0 ie word aligned) */
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#define LE_CSR2 0x0002 /* IADR[23:16] (high bits reserved) */
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#define LE_CSR3 0x0003 /* Misc */
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/*
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* Bit definitions for CSR0 (LANCE Controller Status)
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*/
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#define LE_C0_ERR 0x8000 /* Error = BABL | CERR | MISS | MERR */
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#define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */
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#define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */
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#define LE_C0_MISS 0x1000 /* Missed Frame (no rx buffer to put it in) */
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#define LE_C0_MERR 0x0800 /* Memory Error */
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#define LE_C0_RINT 0x0400 /* Receive Interrupt */
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#define LE_C0_TINT 0x0200 /* Transmit Interrupt */
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#define LE_C0_IDON 0x0100 /* Initialization Done */
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#define LE_C0_INTR 0x0080 /* Interrupt Flag
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= BABL | MISS | MERR | RINT | TINT | IDON */
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#define LE_C0_INEA 0x0040 /* Interrupt Enable */
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#define LE_C0_RXON 0x0020 /* Receive On */
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#define LE_C0_TXON 0x0010 /* Transmit On */
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#define LE_C0_TDMD 0x0008 /* Transmit Demand */
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#define LE_C0_STOP 0x0004 /* Stop */
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#define LE_C0_STRT 0x0002 /* Start */
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#define LE_C0_INIT 0x0001 /* Initialize */
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/*
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* Bit definitions for CSR3
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*/
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#define LE_C3_BSWP 0x0004 /* Byte Swap
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(on for big endian byte order) */
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#define LE_C3_ACON 0x0002 /* ALE Control
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(on for active low ALE) */
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#define LE_C3_BCON 0x0001 /* Byte Control */
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/*
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* Mode Flags
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*/
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#define LE_MO_PROM 0x8000 /* Promiscuous Mode */
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/* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990,
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* but they are in NetBSD's am7990.h, presumably for backwards-compatible chips
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*/
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#define LE_MO_DRCVBC 0x4000 /* disable receive broadcast */
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#define LE_MO_DRCVPA 0x2000 /* disable physical address detection */
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#define LE_MO_DLNKTST 0x1000 /* disable link status */
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#define LE_MO_DAPC 0x0800 /* disable automatic polarity correction */
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#define LE_MO_MENDECL 0x0400 /* MENDEC loopback mode */
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#define LE_MO_LRTTSEL 0x0200 /* lower RX threshold / TX mode selection */
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#define LE_MO_PSEL1 0x0100 /* port selection bit1 */
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#define LE_MO_PSEL0 0x0080 /* port selection bit0 */
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/* and this one is from the C-LANCE data sheet... */
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#define LE_MO_EMBA 0x0080 /* Enable Modified Backoff Algorithm
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(C-LANCE, not original LANCE) */
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#define LE_MO_INTL 0x0040 /* Internal Loopback */
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#define LE_MO_DRTY 0x0020 /* Disable Retry */
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#define LE_MO_FCOLL 0x0010 /* Force Collision */
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#define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */
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#define LE_MO_LOOP 0x0004 /* Loopback Enable */
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#define LE_MO_DTX 0x0002 /* Disable Transmitter */
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#define LE_MO_DRX 0x0001 /* Disable Receiver */
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/*
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* Receive Flags
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*/
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#define LE_R1_OWN 0x80 /* LANCE owns the descriptor */
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#define LE_R1_ERR 0x40 /* Error */
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#define LE_R1_FRA 0x20 /* Framing Error */
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#define LE_R1_OFL 0x10 /* Overflow Error */
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#define LE_R1_CRC 0x08 /* CRC Error */
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#define LE_R1_BUF 0x04 /* Buffer Error */
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#define LE_R1_SOP 0x02 /* Start of Packet */
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#define LE_R1_EOP 0x01 /* End of Packet */
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#define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
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/*
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* Transmit Flags
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*/
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#define LE_T1_OWN 0x80 /* LANCE owns the descriptor */
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#define LE_T1_ERR 0x40 /* Error */
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#define LE_T1_RES 0x20 /* Reserved, LANCE writes this with a zero */
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#define LE_T1_EMORE 0x10 /* More than one retry needed */
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#define LE_T1_EONE 0x08 /* One retry needed */
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#define LE_T1_EDEF 0x04 /* Deferred */
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#define LE_T1_SOP 0x02 /* Start of Packet */
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#define LE_T1_EOP 0x01 /* End of Packet */
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#define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
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/*
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* Error Flags
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*/
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#define LE_T3_BUF 0x8000 /* Buffer Error */
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#define LE_T3_UFL 0x4000 /* Underflow Error */
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#define LE_T3_LCOL 0x1000 /* Late Collision */
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#define LE_T3_CLOS 0x0800 /* Loss of Carrier */
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#define LE_T3_RTY 0x0400 /* Retry Error */
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#define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */
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/* Miscellaneous useful macros */
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#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
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lp->tx_old+lp->tx_ring_mod_mask-lp->tx_new:\
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lp->tx_old - lp->tx_new-1)
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/* The LANCE only uses 24 bit addresses. This does the obvious thing. */
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#define LANCE_ADDR(x) ((int)(x) & ~0xff000000)
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/* Now the prototypes we export */
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extern int lance_open(struct net_device *dev);
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extern int lance_close (struct net_device *dev);
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extern int lance_start_xmit (struct sk_buff *skb, struct net_device *dev);
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extern void lance_set_multicast (struct net_device *dev);
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extern void lance_tx_timeout(struct net_device *dev);
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#ifdef CONFIG_NET_POLL_CONTROLLER
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extern void lance_poll(struct net_device *dev);
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#endif
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#endif /* ndef _7990_H */
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