 a135eaae52
			
		
	
	
	a135eaae52
	
	
	
		
			
			Remove arch/arm/plat-omap/include/plat/clock.h by merging it into arch/arm/mach-omap1/clock.h and arch/arm/mach-omap2/clock.h. The goal here is to facilitate ARM single image kernels by removing includes via the "plat/" symlink. Signed-off-by: Paul Walmsley <paul@pwsan.com> [tony@atomide.com: fixed to remove duplicate clock.h includes] Signed-off-by: Tony Lindgren <tony@atomide.com>
		
			
				
	
	
		
			299 lines
		
	
	
	
		
			6.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			299 lines
		
	
	
	
		
			6.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * SDRC register values for Nokia boards
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|  *
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|  * Copyright (C) 2008, 2010-2011 Nokia Corporation
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|  *
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|  * Lauri Leukkunen <lauri.leukkunen@nokia.com>
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|  *
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|  * Original code by Juha Yrjola <juha.yrjola@solidboot.com>
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  */
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| 
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| #include <linux/kernel.h>
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| #include <linux/clk.h>
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| #include <linux/err.h>
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| #include <linux/io.h>
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| 
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| #include "common.h"
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| #include "sdram-nokia.h"
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| #include "sdrc.h"
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| 
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| /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
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| struct sdram_timings {
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| 	u32 casl;
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| 	u32 tDAL;
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| 	u32 tDPL;
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| 	u32 tRRD;
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| 	u32 tRCD;
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| 	u32 tRP;
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| 	u32 tRAS;
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| 	u32 tRC;
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| 	u32 tRFC;
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| 	u32 tXSR;
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| 
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| 	u32 tREF; /* in ns */
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| 
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| 	u32 tXP;
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| 	u32 tCKE;
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| 	u32 tWTR;
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| };
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| 
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| static const struct sdram_timings nokia_97dot6mhz_timings[] = {
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| 	{
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| 		.casl = 3,
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| 		.tDAL = 30725,
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| 		.tDPL = 15362,
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| 		.tRRD = 10241,
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| 		.tRCD = 20483,
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| 		.tRP = 15362,
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| 		.tRAS = 40967,
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| 		.tRC = 56330,
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| 		.tRFC = 138266,
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| 		.tXSR = 204839,
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| 
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| 		.tREF = 7798,
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| 
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| 		.tXP = 2,
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| 		.tCKE = 4,
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| 		.tWTR = 2,
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| 	},
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| };
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| 
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| static const struct sdram_timings nokia_166mhz_timings[] = {
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| 	{
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| 		.casl = 3,
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| 		.tDAL = 33000,
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| 		.tDPL = 15000,
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| 		.tRRD = 12000,
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| 		.tRCD = 22500,
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| 		.tRP = 18000,
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| 		.tRAS = 42000,
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| 		.tRC = 66000,
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| 		.tRFC = 138000,
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| 		.tXSR = 200000,
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| 
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| 		.tREF = 7800,
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| 
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| 		.tXP = 2,
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| 		.tCKE = 2,
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| 		.tWTR = 2
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| 	},
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| };
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| 
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| static const struct sdram_timings nokia_195dot2mhz_timings[] = {
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| 	{
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| 		.casl = 3,
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| 		.tDAL = 30725,
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| 		.tDPL = 15362,
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| 		.tRRD = 10241,
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| 		.tRCD = 20483,
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| 		.tRP = 15362,
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| 		.tRAS = 40967,
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| 		.tRC = 56330,
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| 		.tRFC = 138266,
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| 		.tXSR = 204839,
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| 
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| 		.tREF = 7752,
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| 
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| 		.tXP = 2,
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| 		.tCKE = 4,
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| 		.tWTR = 2,
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| 	},
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| };
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| 
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| static const struct sdram_timings nokia_200mhz_timings[] = {
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| 	{
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| 		.casl = 3,
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| 		.tDAL = 30000,
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| 		.tDPL = 15000,
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| 		.tRRD = 10000,
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| 		.tRCD = 20000,
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| 		.tRP = 15000,
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| 		.tRAS = 40000,
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| 		.tRC = 55000,
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| 		.tRFC = 140000,
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| 		.tXSR = 200000,
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| 
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| 		.tREF = 7800,
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| 
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| 		.tXP = 2,
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| 		.tCKE = 4,
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| 		.tWTR = 2
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| 	},
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| };
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| 
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| static const struct {
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| 	long rate;
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| 	struct sdram_timings const *data;
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| } nokia_timings[] = {
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| 	{ 83000000, nokia_166mhz_timings },
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| 	{ 97600000, nokia_97dot6mhz_timings },
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| 	{ 100000000, nokia_200mhz_timings },
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| 	{ 166000000, nokia_166mhz_timings },
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| 	{ 195200000, nokia_195dot2mhz_timings },
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| 	{ 200000000, nokia_200mhz_timings },
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| };
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| static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
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| 
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| static unsigned long sdrc_get_fclk_period(long rate)
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| {
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| 	/* In picoseconds */
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| 	return 1000000000 / rate;
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| }
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| 
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| static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate)
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| {
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| 	unsigned long tick_ps;
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| 
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| 	/* Calculate in picosecs to yield more exact results */
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| 	tick_ps = sdrc_get_fclk_period(rate);
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| 
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| 	return (time_ps + tick_ps - 1) / tick_ps;
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| }
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| #undef DEBUG
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| #ifdef DEBUG
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| static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
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| 				int ticks, long rate, const char *name)
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| #else
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| static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
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| 			       int ticks)
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| #endif
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| {
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| 	int mask, nr_bits;
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| 
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| 	nr_bits = end_bit - st_bit + 1;
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| 	if (ticks >= 1 << nr_bits)
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| 		return -1;
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| 	mask = (1 << nr_bits) - 1;
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| 	*regval &= ~(mask << st_bit);
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| 	*regval |= ticks << st_bit;
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| #ifdef DEBUG
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| 	printk(KERN_INFO "SDRC %s: %i ticks %i ns\n", name, ticks,
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| 			(unsigned int)sdrc_get_fclk_period(rate) * ticks /
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| 			1000);
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| #endif
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| 
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| 	return 0;
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| }
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| 
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| #ifdef DEBUG
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| #define SDRC_SET_ONE(reg, st, end, field, rate) \
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| 	if (set_sdrc_timing_regval((reg), (st), (end), \
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| 			memory_timings->field, (rate), #field) < 0) \
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| 		err = -1;
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| #else
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| #define SDRC_SET_ONE(reg, st, end, field, rate) \
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| 	if (set_sdrc_timing_regval((reg), (st), (end), \
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| 			memory_timings->field) < 0) \
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| 		err = -1;
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| #endif
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| 
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| #ifdef DEBUG
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| static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
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| 				int time, long rate, const char *name)
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| #else
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| static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
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| 				int time, long rate)
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| #endif
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| {
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| 	int ticks, ret;
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| 	ret = 0;
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| 
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| 	if (time == 0)
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| 		ticks = 0;
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| 	else
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| 		ticks = sdrc_ps_to_ticks(time, rate);
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| 
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| #ifdef DEBUG
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| 	ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks,
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| 				     rate, name);
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| #else
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| 	ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks);
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| #endif
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| 
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| 	return ret;
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| }
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| 
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| #ifdef DEBUG
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| #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
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| 	if (set_sdrc_timing_regval_ps((reg), (st), (end), \
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| 			memory_timings->field, \
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| 			(rate), #field) < 0) \
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| 		err = -1;
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| 
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| #else
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| #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
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| 	if (set_sdrc_timing_regval_ps((reg), (st), (end), \
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| 			memory_timings->field, (rate)) < 0) \
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| 		err = -1;
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| #endif
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| 
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| static int sdrc_timings(int id, long rate,
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| 			const struct sdram_timings *memory_timings)
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| {
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| 	u32 ticks_per_ms;
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| 	u32 rfr, l;
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| 	u32 actim_ctrla = 0, actim_ctrlb = 0;
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| 	u32 rfr_ctrl;
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| 	int err = 0;
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| 	long l3_rate = rate / 1000;
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| 
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| 	SDRC_SET_ONE_PS(&actim_ctrla,  0,  4, tDAL, l3_rate);
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| 	SDRC_SET_ONE_PS(&actim_ctrla,  6,  8, tDPL, l3_rate);
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| 	SDRC_SET_ONE_PS(&actim_ctrla,  9, 11, tRRD, l3_rate);
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| 	SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate);
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| 	SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate);
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| 	SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate);
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| 	SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate);
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| 	SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate);
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| 
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| 	SDRC_SET_ONE_PS(&actim_ctrlb,  0,  7, tXSR, l3_rate);
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| 
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| 	SDRC_SET_ONE(&actim_ctrlb,  8, 10, tXP, l3_rate);
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| 	SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate);
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| 	SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
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| 
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| 	ticks_per_ms = l3_rate;
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| 	rfr = memory_timings[0].tREF * ticks_per_ms / 1000000;
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| 	if (rfr > 65535 + 50)
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| 		rfr = 65535;
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| 	else
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| 		rfr -= 50;
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| 
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| #ifdef DEBUG
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| 	printk(KERN_INFO "SDRC tREF: %i ticks\n", rfr);
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| #endif
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| 
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| 	l = rfr << 8;
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| 	rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
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| 
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| 	nokia_sdrc_params[id].rate = rate;
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| 	nokia_sdrc_params[id].actim_ctrla = actim_ctrla;
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| 	nokia_sdrc_params[id].actim_ctrlb = actim_ctrlb;
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| 	nokia_sdrc_params[id].rfr_ctrl = rfr_ctrl;
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| 	nokia_sdrc_params[id].mr = 0x32;
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| 
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| 	nokia_sdrc_params[id + 1].rate = 0;
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| 
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| 	return err;
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| }
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| 
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| struct omap_sdrc_params *nokia_get_sdram_timings(void)
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| {
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| 	int err = 0;
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| 	int i;
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| 
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| 	for (i = 0; i < ARRAY_SIZE(nokia_timings); i++) {
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| 		err |= sdrc_timings(i, nokia_timings[i].rate,
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| 				       nokia_timings[i].data);
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| 		if (err)
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| 			pr_err("%s: error with rate %ld: %d\n", __func__,
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| 			       nokia_timings[i].rate, err);
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| 	}
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| 
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| 	return err ? NULL : nokia_sdrc_params;
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| }
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| 
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