1306c08a7c
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688. omap_bus_sync will be NOP until SRAM initialization happens. Suggested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
282 lines
6.4 KiB
C
282 lines
6.4 KiB
C
/*
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* OMAP4 specific common source file.
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/platform_device.h>
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#include <linux/memblock.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/export.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/irq-crossbar.h>
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#include <linux/of_address.h>
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#include <linux/reboot.h>
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#include <linux/genalloc.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/map.h>
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#include <asm/memblock.h>
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#include <asm/smp_twd.h>
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#include "omap-wakeupgen.h"
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#include "soc.h"
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#include "iomap.h"
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#include "common.h"
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#include "mmc.h"
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#include "prminst44xx.h"
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#include "prcm_mpu44xx.h"
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#include "omap4-sar-layout.h"
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#include "omap-secure.h"
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#include "sram.h"
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#ifdef CONFIG_CACHE_L2X0
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static void __iomem *l2cache_base;
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#endif
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static void __iomem *sar_ram_base;
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static void __iomem *gic_dist_base_addr;
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static void __iomem *twd_base;
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#define IRQ_LOCALTIMER 29
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#ifdef CONFIG_OMAP4_ERRATA_I688
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/* Used to implement memory barrier on DRAM path */
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#define OMAP4_DRAM_BARRIER_VA 0xfe600000
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void __iomem *dram_sync, *sram_sync;
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static phys_addr_t paddr;
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static u32 size;
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void omap_bus_sync(void)
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{
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if (dram_sync && sram_sync) {
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writel_relaxed(readl_relaxed(dram_sync), dram_sync);
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writel_relaxed(readl_relaxed(sram_sync), sram_sync);
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isb();
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}
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}
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EXPORT_SYMBOL(omap_bus_sync);
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static int __init omap4_sram_init(void)
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{
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struct device_node *np;
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struct gen_pool *sram_pool;
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np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
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if (!np)
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pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
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__func__);
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sram_pool = of_get_named_gen_pool(np, "sram", 0);
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if (!sram_pool)
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pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
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__func__);
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else
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sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
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return 0;
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}
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omap_arch_initcall(omap4_sram_init);
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/* Steal one page physical memory for barrier implementation */
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int __init omap_barrier_reserve_memblock(void)
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{
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size = ALIGN(PAGE_SIZE, SZ_1M);
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paddr = arm_memblock_steal(size, SZ_1M);
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return 0;
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}
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void __init omap_barriers_init(void)
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{
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struct map_desc dram_io_desc[1];
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dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
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dram_io_desc[0].pfn = __phys_to_pfn(paddr);
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dram_io_desc[0].length = size;
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dram_io_desc[0].type = MT_MEMORY_RW_SO;
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iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
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dram_sync = (void __iomem *) dram_io_desc[0].virtual;
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pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
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(long long) paddr, dram_io_desc[0].virtual);
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}
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#else
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void __init omap_barriers_init(void)
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{}
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#endif
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void gic_dist_disable(void)
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{
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if (gic_dist_base_addr)
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writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
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}
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void gic_dist_enable(void)
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{
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if (gic_dist_base_addr)
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writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
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}
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bool gic_dist_disabled(void)
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{
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return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
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}
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void gic_timer_retrigger(void)
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{
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u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
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u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
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u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
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if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
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/*
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* The local timer interrupt got lost while the distributor was
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* disabled. Ack the pending interrupt, and retrigger it.
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*/
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pr_warn("%s: lost localtimer interrupt\n", __func__);
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writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
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if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
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writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
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twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
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writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
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}
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}
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}
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *omap4_get_l2cache_base(void)
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{
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return l2cache_base;
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}
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static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
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{
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unsigned smc_op;
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switch (reg) {
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case L2X0_CTRL:
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smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
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break;
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case L2X0_AUX_CTRL:
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smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
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break;
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case L2X0_DEBUG_CTRL:
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smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
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break;
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case L310_PREFETCH_CTRL:
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smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
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break;
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case L310_POWER_CTRL:
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pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
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return;
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default:
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WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
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return;
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}
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omap_smc1(smc_op, val);
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}
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int __init omap_l2_cache_init(void)
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{
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u32 aux_ctrl;
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/* Static mapping, never released */
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l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
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if (WARN_ON(!l2cache_base))
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return -ENOMEM;
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/* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
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aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
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L310_AUX_CTRL_DATA_PREFETCH |
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L310_AUX_CTRL_INSTR_PREFETCH;
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outer_cache.write_sec = omap4_l2c310_write_sec;
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if (of_have_populated_dt())
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l2x0_of_init(aux_ctrl, 0xcf9fffff);
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else
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l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);
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return 0;
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}
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#endif
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void __iomem *omap4_get_sar_ram_base(void)
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{
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return sar_ram_base;
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}
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/*
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* SAR RAM used to save and restore the HW
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* context in low power modes
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*/
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static int __init omap4_sar_ram_init(void)
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{
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unsigned long sar_base;
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/*
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* To avoid code running on other OMAPs in
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* multi-omap builds
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*/
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if (cpu_is_omap44xx())
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sar_base = OMAP44XX_SAR_RAM_BASE;
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else if (soc_is_omap54xx())
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sar_base = OMAP54XX_SAR_RAM_BASE;
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else
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return -ENOMEM;
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/* Static mapping, never released */
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sar_ram_base = ioremap(sar_base, SZ_16K);
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if (WARN_ON(!sar_ram_base))
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return -ENOMEM;
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return 0;
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}
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omap_early_initcall(omap4_sar_ram_init);
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void __init omap_gic_of_init(void)
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{
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struct device_node *np;
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/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
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if (!cpu_is_omap446x())
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goto skip_errata_init;
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
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gic_dist_base_addr = of_iomap(np, 0);
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WARN_ON(!gic_dist_base_addr);
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
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twd_base = of_iomap(np, 0);
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WARN_ON(!twd_base);
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skip_errata_init:
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omap_wakeupgen_init();
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#ifdef CONFIG_IRQ_CROSSBAR
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irqcrossbar_init();
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#endif
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irqchip_init();
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}
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