233df5d124
This patch encloses sam9n12 old clk registration in "#if defined(CONFIG_OLD_CLK_AT91) #endif" sections. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Tested-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
241 lines
6.1 KiB
C
241 lines
6.1 KiB
C
/*
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* SoC specific setup code for the AT91SAM9N12
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*
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* Copyright (C) 2012 Atmel Corporation.
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk/at91_pmc.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/at91sam9n12.h>
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#include <mach/cpu.h>
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#include "board.h"
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#include "soc.h"
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#include "generic.h"
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#include "sam9_smc.h"
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#if defined(CONFIG_OLD_CLK_AT91)
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#include "clock.h"
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/* --------------------------------------------------------------------
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* Clocks
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* -------------------------------------------------------------------- */
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/*
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* The peripheral clocks.
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*/
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static struct clk pioAB_clk = {
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.name = "pioAB_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pioCD_clk = {
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.name = "pioCD_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart0_clk = {
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.name = "usart0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_USART0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart1_clk = {
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.name = "usart1_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_USART1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart2_clk = {
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.name = "usart2_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_USART2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk usart3_clk = {
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.name = "usart3_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_USART3,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi0_clk = {
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.name = "twi0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk twi1_clk = {
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.name = "twi1_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk mmc_clk = {
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.name = "mci_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_MCI,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi0_clk = {
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.name = "spi0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk spi1_clk = {
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.name = "spi1_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uart0_clk = {
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.name = "uart0_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_UART0,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uart1_clk = {
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.name = "uart1_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_UART1,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk tcb_clk = {
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.name = "tcb_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_PWM,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk adc_clk = {
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.name = "adc_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_ADC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk dma_clk = {
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.name = "dma_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_DMA,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk uhp_clk = {
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.name = "uhp",
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.pmc_mask = 1 << AT91SAM9N12_ID_UHP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk udp_clk = {
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.name = "udp_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_UDP,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk lcdc_clk = {
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.name = "lcdc_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk ssc_clk = {
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.name = "ssc_clk",
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.pmc_mask = 1 << AT91SAM9N12_ID_SSC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk *periph_clocks[] __initdata = {
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&pioAB_clk,
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&pioCD_clk,
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&usart0_clk,
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&usart1_clk,
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&usart2_clk,
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&usart3_clk,
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&twi0_clk,
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&twi1_clk,
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&mmc_clk,
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&spi0_clk,
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&spi1_clk,
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&lcdc_clk,
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&uart0_clk,
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&uart1_clk,
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&tcb_clk,
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&pwm_clk,
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&adc_clk,
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&dma_clk,
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&uhp_clk,
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&udp_clk,
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&ssc_clk,
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};
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static struct clk_lookup periph_clocks_lookups[] = {
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/* lookup table for DT entries */
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CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
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CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
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CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
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CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
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CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
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CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
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CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
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CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk),
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CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
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CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
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CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
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CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
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CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
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/* additional fake clock for macb_hclk */
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CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
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CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
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CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
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};
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/*
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* The two programmable clocks.
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* You must configure pin multiplexing to bring these signals out.
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*/
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static struct clk pck0 = {
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.name = "pck0",
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.pmc_mask = AT91_PMC_PCK0,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 0,
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};
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static struct clk pck1 = {
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.name = "pck1",
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.pmc_mask = AT91_PMC_PCK1,
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.type = CLK_TYPE_PROGRAMMABLE,
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.id = 1,
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};
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static void __init at91sam9n12_register_clocks(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
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clk_register(periph_clocks[i]);
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clk_register(&pck0);
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clk_register(&pck1);
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clkdev_add_table(periph_clocks_lookups,
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ARRAY_SIZE(periph_clocks_lookups));
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}
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#else
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#define at91sam9n12_register_clocks NULL
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#endif
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/* --------------------------------------------------------------------
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* AT91SAM9N12 processor initialization
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* -------------------------------------------------------------------- */
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static void __init at91sam9n12_map_io(void)
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{
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at91_init_sram(0, AT91SAM9N12_SRAM_BASE, AT91SAM9N12_SRAM_SIZE);
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}
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static void __init at91sam9n12_initialize(void)
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{
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at91_sysirq_mask_rtc(AT91SAM9N12_BASE_RTC);
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}
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AT91_SOC_START(at91sam9n12)
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.map_io = at91sam9n12_map_io,
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.register_clocks = at91sam9n12_register_clocks,
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.init = at91sam9n12_initialize,
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AT91_SOC_END
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