 4b3e2edacf
			
		
	
	
	4b3e2edacf
	
	
	
		
			
			There are some Tegra SoC ID checking code around the low level assembly code. Adding a marco to replace them. For the single image to support all the Tegra series, we may also need the marco in other common code. So we make it become a marco for the usage. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
		
			
				
	
	
		
			78 lines
		
	
	
	
		
			1.9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			78 lines
		
	
	
	
		
			1.9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Copyright (C) 2010 Google, Inc.
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|  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
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|  *
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|  * Author:
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|  *	Colin Cross <ccross@android.com>
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|  *
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|  * This software is licensed under the terms of the GNU General Public
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|  * License version 2, as published by the Free Software Foundation, and
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|  * may be copied, distributed, and modified under those terms.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  */
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| 
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| #ifndef __MACH_TEGRA_FUSE_H
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| #define __MACH_TEGRA_FUSE_H
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| 
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| #define SKU_ID_T20	8
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| #define SKU_ID_T25SE	20
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| #define SKU_ID_AP25	23
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| #define SKU_ID_T25	24
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| #define SKU_ID_AP25E	27
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| #define SKU_ID_T25E	28
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| 
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| #define TEGRA20		0x20
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| #define TEGRA30		0x30
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| #define TEGRA114	0x35
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| 
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| #ifndef __ASSEMBLY__
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| enum tegra_revision {
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| 	TEGRA_REVISION_UNKNOWN = 0,
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| 	TEGRA_REVISION_A01,
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| 	TEGRA_REVISION_A02,
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| 	TEGRA_REVISION_A03,
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| 	TEGRA_REVISION_A03p,
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| 	TEGRA_REVISION_A04,
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| 	TEGRA_REVISION_MAX,
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| };
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| 
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| extern int tegra_sku_id;
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| extern int tegra_cpu_process_id;
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| extern int tegra_core_process_id;
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| extern int tegra_chip_id;
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| extern int tegra_cpu_speedo_id;		/* only exist in Tegra30 and later */
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| extern int tegra_soc_speedo_id;
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| extern enum tegra_revision tegra_revision;
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| 
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| extern int tegra_bct_strapping;
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| 
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| unsigned long long tegra_chip_uid(void);
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| void tegra_init_fuse(void);
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| bool tegra_spare_fuse(int bit);
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| u32 tegra_fuse_readl(unsigned long offset);
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| 
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| #ifdef CONFIG_ARCH_TEGRA_2x_SOC
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| void tegra20_init_speedo_data(void);
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| #else
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| static inline void tegra20_init_speedo_data(void) {}
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| #endif
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| 
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| #ifdef CONFIG_ARCH_TEGRA_3x_SOC
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| void tegra30_init_speedo_data(void);
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| #else
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| static inline void tegra30_init_speedo_data(void) {}
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| #endif
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| 
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| #ifdef CONFIG_ARCH_TEGRA_114_SOC
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| void tegra114_init_speedo_data(void);
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| #else
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| static inline void tegra114_init_speedo_data(void) {}
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| #endif
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| #endif /* __ASSEMBLY__ */
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| 
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| #endif
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