Pull ARM updates from Russell King:
"This contains the usual updates from other people (listed below) and
the usual random muddle of miscellaneous ARM updates which cover some
low priority bug fixes and performance improvements.
I've started to put the pull request wording into the merge commits,
which are:
- NoMMU stuff:
This includes the following series sent earlier to the list:
- nommu-fixes
- R7 Support
- MPU support
I've left out the ARCH_MULTIPLATFORM/!MMU stuff that Arnd and I
were discussing today until we've reached a conclusion/that's had
some more review.
This is rebased (and re-tested) on your devel-stable branch because
otherwise there were going to be conflicts with Uwe's V7M work now
that you've merged that. I've included the fix for limiting MPU to
CPU_V7.
- Huge page support
These changes bring both HugeTLB support and Transparent HugePage
(THP) support to ARM. Only long descriptors (LPAE) are supported
in this series.
The code has been tested on an Arndale board (Exynos 5250).
- LPAE updates
Please pull these miscellaneous LPAE fixes I've been collecting for
a while now for 3.11. They've been tested and reviewed by quite a
few people, and most of the patches are pretty trivial. -- Will Deacon.
- arch_timer cleanups
Please pull these arch_timer cleanups I've been holding onto for a
while. They're the same as my last posting, but have been rebased
to v3.10-rc3.
- mpidr linearisation (multiprocessor id register - identifies which
CPU number we are in the system)
This patch series that implements MPIDR linearization through a
simple hashing algorithm and updates current cpu_{suspend}/{resume}
code to use the newly created hash structures to retrieve context
pointers. It represents a stepping stone for the implementation of
power management code on forthcoming multi-cluster ARM systems.
It has been tested on TC2 (dual cluster A15xA7 system), iMX6q,
OMAP4 and Tegra, with processors hitting low-power states requiring
warm-boot resume through the cpu_resume code path"
* 'for-linus' of git://git.linaro.org/people/rmk/linux-arm: (77 commits)
ARM: 7775/1: mm: Remove do_sect_fault from LPAE code
ARM: 7777/1: Avoid extra calls to the C compiler
ARM: 7774/1: Fix dtb dependency to use order-only prerequisites
ARM: 7770/1: remove residual ARMv2 support from decompressor
ARM: 7769/1: Cortex-A15: fix erratum 798181 implementation
ARM: 7768/1: prevent risks of out-of-bound access in ASID allocator
ARM: 7767/1: let the ASID allocator handle suspended animation
ARM: 7766/1: versatile: don't mark pen as __INIT
ARM: 7765/1: perf: Record the user-mode PC in the call chain.
ARM: 7735/2: Preserve the user r/w register TPIDRURW on context switch and fork
ARM: kernel: implement stack pointer save array through MPIDR hashing
ARM: kernel: build MPIDR hash function data structure
ARM: mpu: Ensure that MPU depends on CPU_V7
ARM: mpu: protect the vectors page with an MPU region
ARM: mpu: Allow enabling of the MPU via kconfig
ARM: 7758/1: introduce config HAS_BANDGAP
ARM: 7757/1: mm: don't flush icache in switch_mm with hardware broadcasting
ARM: 7751/1: zImage: don't overwrite ourself with a page table
ARM: 7749/1: spinlock: retry trylock operation if strex fails on free lock
ARM: 7748/1: oabi: handle faults when loading swi instruction from userspace
...
184 lines
5.1 KiB
C
184 lines
5.1 KiB
C
/* arch/arm/mach-msm/io.c
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*
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* MSM7K, QSD io support
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <mach/hardware.h>
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#include <asm/page.h>
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#include <mach/msm_iomap.h>
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#include <asm/mach/map.h>
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#include <mach/board.h>
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#include "common.h"
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#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
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.virtual = (unsigned long) MSM_##name##_BASE, \
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.pfn = __phys_to_pfn(chip##_##name##_PHYS), \
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.length = chip##_##name##_SIZE, \
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.type = mem_type, \
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}
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#define MSM_DEVICE_TYPE(name, mem_type) \
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MSM_CHIP_DEVICE_TYPE(name, MSM, mem_type)
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#define MSM_CHIP_DEVICE(name, chip) \
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MSM_CHIP_DEVICE_TYPE(name, chip, MT_DEVICE)
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#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
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#if defined(CONFIG_ARCH_MSM7X00A)
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static struct map_desc msm_io_desc[] __initdata = {
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MSM_DEVICE_TYPE(VIC, MT_DEVICE_NONSHARED),
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MSM_CHIP_DEVICE_TYPE(CSR, MSM7X00, MT_DEVICE_NONSHARED),
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MSM_DEVICE_TYPE(DMOV, MT_DEVICE_NONSHARED),
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MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
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MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
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MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
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#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
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defined(CONFIG_DEBUG_MSM_UART3)
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MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
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#endif
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{
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.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
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.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
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.length = MSM_SHARED_RAM_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init msm_map_common_io(void)
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{
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/* Make sure the peripheral register window is closed, since
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* we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
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* pages are peripheral interface or not.
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*/
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asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
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iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc));
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}
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#endif
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#ifdef CONFIG_ARCH_QSD8X50
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static struct map_desc qsd8x50_io_desc[] __initdata = {
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MSM_DEVICE(VIC),
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MSM_CHIP_DEVICE(CSR, QSD8X50),
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MSM_DEVICE(DMOV),
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MSM_CHIP_DEVICE(GPIO1, QSD8X50),
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MSM_CHIP_DEVICE(GPIO2, QSD8X50),
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MSM_DEVICE(CLK_CTL),
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MSM_DEVICE(SIRC),
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MSM_DEVICE(SCPLL),
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MSM_DEVICE(AD5),
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MSM_DEVICE(MDC),
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#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
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defined(CONFIG_DEBUG_MSM_UART3)
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MSM_DEVICE(DEBUG_UART),
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#endif
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{
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.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
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.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
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.length = MSM_SHARED_RAM_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init msm_map_qsd8x50_io(void)
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{
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iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
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}
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#endif /* CONFIG_ARCH_QSD8X50 */
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#ifdef CONFIG_ARCH_MSM8X60
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static struct map_desc msm8x60_io_desc[] __initdata = {
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MSM_CHIP_DEVICE(TMR, MSM8X60),
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MSM_CHIP_DEVICE(TMR0, MSM8X60),
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#ifdef CONFIG_DEBUG_MSM8660_UART
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MSM_DEVICE(DEBUG_UART),
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#endif
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};
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void __init msm_map_msm8x60_io(void)
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{
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iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
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}
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#endif /* CONFIG_ARCH_MSM8X60 */
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#ifdef CONFIG_ARCH_MSM8960
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static struct map_desc msm8960_io_desc[] __initdata = {
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MSM_CHIP_DEVICE(TMR, MSM8960),
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MSM_CHIP_DEVICE(TMR0, MSM8960),
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#ifdef CONFIG_DEBUG_MSM8960_UART
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MSM_DEVICE(DEBUG_UART),
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#endif
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};
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void __init msm_map_msm8960_io(void)
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{
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iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
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}
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#endif /* CONFIG_ARCH_MSM8960 */
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#ifdef CONFIG_ARCH_MSM7X30
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static struct map_desc msm7x30_io_desc[] __initdata = {
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MSM_DEVICE(VIC),
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MSM_CHIP_DEVICE(CSR, MSM7X30),
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MSM_DEVICE(DMOV),
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MSM_CHIP_DEVICE(GPIO1, MSM7X30),
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MSM_CHIP_DEVICE(GPIO2, MSM7X30),
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MSM_DEVICE(CLK_CTL),
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MSM_DEVICE(CLK_CTL_SH2),
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MSM_DEVICE(AD5),
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MSM_DEVICE(MDC),
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MSM_DEVICE(ACC),
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MSM_DEVICE(SAW),
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MSM_DEVICE(GCC),
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MSM_DEVICE(TCSR),
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#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
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defined(CONFIG_DEBUG_MSM_UART3)
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MSM_DEVICE(DEBUG_UART),
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#endif
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{
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.virtual = (unsigned long) MSM_SHARED_RAM_BASE,
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.pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
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.length = MSM_SHARED_RAM_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init msm_map_msm7x30_io(void)
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{
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iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
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}
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#endif /* CONFIG_ARCH_MSM7X30 */
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void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
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unsigned int mtype, void *caller)
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{
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if (mtype == MT_DEVICE) {
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/* The peripherals in the 88000000 - D0000000 range
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* are only accessible by type MT_DEVICE_NONSHARED.
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* Adjust mtype as necessary to make this "just work."
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*/
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if ((phys_addr >= 0x88000000) && (phys_addr < 0xD0000000))
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mtype = MT_DEVICE_NONSHARED;
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}
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return __arm_ioremap_caller(phys_addr, size, mtype, caller);
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}
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