358aa7031d
When CONFIG_PMB enable, ITLB is not cleared by reset of watchdog timer. This should use trigger_address_error(). Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
272 lines
6.6 KiB
C
272 lines
6.6 KiB
C
#ifndef __ASM_SH_SYSTEM_32_H
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#define __ASM_SH_SYSTEM_32_H
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#include <linux/types.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_SH_DSP
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#define is_dsp_enabled(tsk) \
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(!!(tsk->thread.dsp_status.status & SR_DSP))
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#define __restore_dsp(tsk) \
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do { \
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register u32 *__ts2 __asm__ ("r2") = \
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(u32 *)&tsk->thread.dsp_status; \
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__asm__ __volatile__ ( \
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".balign 4\n\t" \
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"movs.l @r2+, a0\n\t" \
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"movs.l @r2+, a1\n\t" \
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"movs.l @r2+, a0g\n\t" \
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"movs.l @r2+, a1g\n\t" \
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"movs.l @r2+, m0\n\t" \
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"movs.l @r2+, m1\n\t" \
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"movs.l @r2+, x0\n\t" \
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"movs.l @r2+, x1\n\t" \
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"movs.l @r2+, y0\n\t" \
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"movs.l @r2+, y1\n\t" \
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"lds.l @r2+, dsr\n\t" \
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"ldc.l @r2+, rs\n\t" \
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"ldc.l @r2+, re\n\t" \
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"ldc.l @r2+, mod\n\t" \
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: : "r" (__ts2)); \
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} while (0)
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#define __save_dsp(tsk) \
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do { \
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register u32 *__ts2 __asm__ ("r2") = \
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(u32 *)&tsk->thread.dsp_status + 14; \
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\
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__asm__ __volatile__ ( \
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".balign 4\n\t" \
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"stc.l mod, @-r2\n\t" \
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"stc.l re, @-r2\n\t" \
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"stc.l rs, @-r2\n\t" \
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"sts.l dsr, @-r2\n\t" \
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"movs.l y1, @-r2\n\t" \
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"movs.l y0, @-r2\n\t" \
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"movs.l x1, @-r2\n\t" \
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"movs.l x0, @-r2\n\t" \
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"movs.l m1, @-r2\n\t" \
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"movs.l m0, @-r2\n\t" \
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"movs.l a1g, @-r2\n\t" \
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"movs.l a0g, @-r2\n\t" \
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"movs.l a1, @-r2\n\t" \
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"movs.l a0, @-r2\n\t" \
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: : "r" (__ts2)); \
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} while (0)
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#else
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#define is_dsp_enabled(tsk) (0)
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#define __save_dsp(tsk) do { } while (0)
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#define __restore_dsp(tsk) do { } while (0)
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#endif
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#if defined(CONFIG_CPU_SH4A)
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#define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr))
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#else
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#define __icbi(addr) mb()
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#endif
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#define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr))
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#define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr))
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#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr))
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struct task_struct *__switch_to(struct task_struct *prev,
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struct task_struct *next);
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/*
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* switch_to() should switch tasks to task nr n, first
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*/
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#define switch_to(prev, next, last) \
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do { \
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register u32 *__ts1 __asm__ ("r1"); \
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register u32 *__ts2 __asm__ ("r2"); \
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register u32 *__ts4 __asm__ ("r4"); \
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register u32 *__ts5 __asm__ ("r5"); \
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register u32 *__ts6 __asm__ ("r6"); \
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register u32 __ts7 __asm__ ("r7"); \
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struct task_struct *__last; \
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\
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if (is_dsp_enabled(prev)) \
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__save_dsp(prev); \
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\
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__ts1 = (u32 *)&prev->thread.sp; \
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__ts2 = (u32 *)&prev->thread.pc; \
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__ts4 = (u32 *)prev; \
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__ts5 = (u32 *)next; \
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__ts6 = (u32 *)&next->thread.sp; \
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__ts7 = next->thread.pc; \
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\
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__asm__ __volatile__ ( \
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".balign 4\n\t" \
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"stc.l gbr, @-r15\n\t" \
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"sts.l pr, @-r15\n\t" \
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"mov.l r8, @-r15\n\t" \
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"mov.l r9, @-r15\n\t" \
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"mov.l r10, @-r15\n\t" \
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"mov.l r11, @-r15\n\t" \
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"mov.l r12, @-r15\n\t" \
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"mov.l r13, @-r15\n\t" \
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"mov.l r14, @-r15\n\t" \
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"mov.l r15, @r1\t! save SP\n\t" \
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"mov.l @r6, r15\t! change to new stack\n\t" \
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"mova 1f, %0\n\t" \
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"mov.l %0, @r2\t! save PC\n\t" \
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"mov.l 2f, %0\n\t" \
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"jmp @%0\t! call __switch_to\n\t" \
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" lds r7, pr\t! with return to new PC\n\t" \
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".balign 4\n" \
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"2:\n\t" \
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".long __switch_to\n" \
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"1:\n\t" \
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"mov.l @r15+, r14\n\t" \
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"mov.l @r15+, r13\n\t" \
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"mov.l @r15+, r12\n\t" \
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"mov.l @r15+, r11\n\t" \
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"mov.l @r15+, r10\n\t" \
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"mov.l @r15+, r9\n\t" \
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"mov.l @r15+, r8\n\t" \
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"lds.l @r15+, pr\n\t" \
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"ldc.l @r15+, gbr\n\t" \
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: "=z" (__last) \
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: "r" (__ts1), "r" (__ts2), "r" (__ts4), \
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"r" (__ts5), "r" (__ts6), "r" (__ts7) \
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: "r3", "t"); \
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\
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last = __last; \
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} while (0)
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#define finish_arch_switch(prev) \
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do { \
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if (is_dsp_enabled(prev)) \
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__restore_dsp(prev); \
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} while (0)
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/*
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* Jump to uncached area.
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* When handling TLB or caches, we need to do it from an uncached area.
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*/
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#define jump_to_uncached() \
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do { \
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unsigned long __dummy; \
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\
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__asm__ __volatile__( \
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"mova 1f, %0\n\t" \
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"add %1, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1:" \
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: "=&z" (__dummy) \
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: "r" (cached_to_uncached)); \
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} while (0)
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/*
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* Back to cached area.
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*/
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#define back_to_cached() \
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do { \
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unsigned long __dummy; \
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ctrl_barrier(); \
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__asm__ __volatile__( \
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"mov.l 1f, %0\n\t" \
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"jmp @%0\n\t" \
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" nop\n\t" \
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".balign 4\n" \
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"1: .long 2f\n" \
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"2:" \
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: "=&r" (__dummy)); \
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} while (0)
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#ifdef CONFIG_CPU_HAS_SR_RB
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#define lookup_exception_vector() \
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({ \
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unsigned long _vec; \
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\
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__asm__ __volatile__ ( \
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"stc r2_bank, %0\n\t" \
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: "=r" (_vec) \
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); \
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\
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_vec; \
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})
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#else
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#define lookup_exception_vector() \
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({ \
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unsigned long _vec; \
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__asm__ __volatile__ ( \
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"mov r4, %0\n\t" \
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: "=r" (_vec) \
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); \
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\
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_vec; \
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})
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#endif
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static inline reg_size_t register_align(void *val)
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{
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return (unsigned long)(signed long)val;
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}
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int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
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struct mem_access *ma, int);
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static inline void trigger_address_error(void)
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{
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__asm__ __volatile__ (
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"ldc %0, sr\n\t"
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"mov.l @%1, %0"
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:
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: "r" (0x10000000), "r" (0x80000001)
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);
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}
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asmlinkage void do_address_error(struct pt_regs *regs,
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unsigned long writeaccess,
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unsigned long address);
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asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7,
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struct pt_regs __regs);
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asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7,
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struct pt_regs __regs);
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asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7,
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struct pt_regs __regs);
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asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7,
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struct pt_regs __regs);
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static inline void set_bl_bit(void)
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{
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unsigned long __dummy0, __dummy1;
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__asm__ __volatile__ (
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"stc sr, %0\n\t"
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"or %2, %0\n\t"
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"and %3, %0\n\t"
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"ldc %0, sr\n\t"
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: "=&r" (__dummy0), "=r" (__dummy1)
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: "r" (0x10000000), "r" (0xffffff0f)
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: "memory"
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);
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}
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static inline void clear_bl_bit(void)
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{
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unsigned long __dummy0, __dummy1;
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__asm__ __volatile__ (
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"stc sr, %0\n\t"
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"and %2, %0\n\t"
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"ldc %0, sr\n\t"
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: "=&r" (__dummy0), "=r" (__dummy1)
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: "1" (~0x10000000)
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: "memory"
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);
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}
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#endif /* __ASM_SH_SYSTEM_32_H */
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