38973ba790
Make sure we compute CPU addresses (resource start/end) the same way both
when we set up the I/O aperture (hose->io_resource) and when we use
pcibios_bus_to_resource() to convert BAR values into resources.
This fixes a build failure ("cast from pointer to integer of different
size" in configs where resource_size_t is 64 bits but pointers are 32 bits)
I introduced in 6c5705fec6.
Acked-By: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
192 lines
5.5 KiB
C
192 lines
5.5 KiB
C
#ifndef __ASM_POWERPC_PCI_H
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#define __ASM_POWERPC_PCI_H
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#ifdef __KERNEL__
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/dma-mapping.h>
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#include <asm/machdep.h>
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#include <asm/scatterlist.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm-generic/pci-dma-compat.h>
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/* Return values for ppc_md.pci_probe_mode function */
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#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
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#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
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#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x10000000
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struct pci_dev;
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/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
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#define IOBASE_BRIDGE_NUMBER 0
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#define IOBASE_MEMORY 1
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#define IOBASE_IO 2
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#define IOBASE_ISA_IO 3
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#define IOBASE_ISA_MEM 4
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/*
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* Set this to 1 if you want the kernel to re-assign all PCI
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* bus numbers (don't do that on ppc64 yet !)
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*/
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#define pcibios_assign_all_busses() \
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(pci_has_flag(PCI_REASSIGN_ALL_BUS))
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static inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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if (ppc_md.pci_get_legacy_ide_irq)
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return ppc_md.pci_get_legacy_ide_irq(dev, channel);
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return channel ? 15 : 14;
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}
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#ifdef CONFIG_PCI
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extern void set_pci_dma_ops(struct dma_map_ops *dma_ops);
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extern struct dma_map_ops *get_pci_dma_ops(void);
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#else /* CONFIG_PCI */
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#define set_pci_dma_ops(d)
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#define get_pci_dma_ops() NULL
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#endif
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#ifdef CONFIG_PPC64
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/*
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* We want to avoid touching the cacheline size or MWI bit.
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* pSeries firmware sets the cacheline size (which is not the cpu cacheline
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* size in all cases) and hardware treats MWI the same as memory write.
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*/
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#define PCI_DISABLE_MWI
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_MULTIPLE;
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*strategy_parameter = cacheline_size;
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}
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#endif
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#else /* 32-bit */
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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*strat = PCI_DMA_BURST_INFINITY;
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*strategy_parameter = ~0UL;
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}
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#endif
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#endif /* CONFIG_PPC64 */
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extern int pci_domain_nr(struct pci_bus *bus);
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/* Decide whether to display the domain number in /proc */
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extern int pci_proc_domain(struct pci_bus *bus);
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/* MSI arch hooks */
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#define arch_setup_msi_irqs arch_setup_msi_irqs
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#define arch_teardown_msi_irqs arch_teardown_msi_irqs
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#define arch_msi_check_device arch_msi_check_device
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struct vm_area_struct;
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/* Map a range of PCI memory or I/O space for a device into user space */
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int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine);
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/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
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#define HAVE_PCI_MMAP 1
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extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
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size_t count);
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extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
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size_t count);
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extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
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struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state);
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#define HAVE_PCI_LEGACY 1
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#ifdef CONFIG_PPC64
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/* The PCI address space does not equal the physical memory address
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* space (we have an IOMMU). The IDE and SCSI device layers use
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* this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS (0)
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#else /* 32-bit */
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/* The PCI address space does equal the physical memory
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* address space (no IOMMU). The IDE and SCSI device layers use
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* this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS (1)
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#endif /* CONFIG_PPC64 */
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extern void pcibios_claim_one_bus(struct pci_bus *b);
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extern void pcibios_finish_adding_to_bus(struct pci_bus *bus);
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extern void pcibios_resource_survey(void);
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extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
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extern int remove_phb_dynamic(struct pci_controller *phb);
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extern struct pci_dev *of_create_pci_dev(struct device_node *node,
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struct pci_bus *bus, int devfn);
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extern void of_scan_pci_bridge(struct pci_dev *dev);
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extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
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extern void of_rescan_bus(struct device_node *node, struct pci_bus *bus);
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struct file;
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extern pgprot_t pci_phys_mem_access_prot(struct file *file,
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unsigned long pfn,
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unsigned long size,
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pgprot_t prot);
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#define HAVE_ARCH_PCI_RESOURCE_TO_USER
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extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
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const struct resource *rsrc,
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resource_size_t *start, resource_size_t *end);
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extern resource_size_t pcibios_io_space_offset(struct pci_controller *hose);
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extern void pcibios_setup_bus_devices(struct pci_bus *bus);
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extern void pcibios_setup_bus_self(struct pci_bus *bus);
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extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
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extern void pcibios_scan_phb(struct pci_controller *hose);
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#endif /* __KERNEL__ */
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#endif /* __ASM_POWERPC_PCI_H */
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