eaed435a7b
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJPFmj/AAoJEIwa5zzehBx3utoP/2JKstlluwVdoIjzLDwJIZWS
BiFO90iC6knKHb3c4ZXBNtD4yz8ImFGr2v3IY4pR+feECu+zS/AYeynrr4AjlaRj
2wHI3/Cl2VktlzUR0k1KqfNrt1HLpZ8myxJ/pKchU8+KnxeQwCdV7MzkxocO0Abs
BQFhXj2WuS6b+H3kObrTy7n3tIyVeGUOW/bPU9TfWeRYEWBpGlqtPOH6A2cGi5e3
Iu9d9MPAiMt33+e7wZdmVHFky+ueqqeKevev+Vt8/JSJbPO7EseS/sbTOZH7Q1Yc
BWe5iARFpV9viJJMlwlO+wJ08BrqzCZ6M/mBITMAZ+a/EMYRn0TwibsWDw1GcAsA
H04Z1TW7pjni7SNFJavW3YWIR3TAKDZqwWbekGl2RzYqKmer1Hk6gwHAhxDQlMGY
2S7dSnw97zRA0WxW6kMPw5VY9VpDD1qjW+29UpEEePfAVhKkwE+lKYlX4k/l0ElC
9iYNoMVlhS4d5A7ZvhNU28XyGoxzAPNA4nC5OMUARZN++oSURDJ1kGNc73WQ8IbG
x+zZ7AFvt7y8OgZqG4bE+SeiHlYVAjtyV08WLxtDx4vTyNYuiWIXguf2hLJWEJPY
sqPGFHrMeh9YvYOXaa+DFb0fPkBJVJt663FPZ4TG2UBlphi26Ax5FtcnSBBvY4QV
CCen+xhdxX/dp83A/A0k
=ZgSs
-----END PGP SIGNATURE-----
Merge tag 'arm-soc-imx-move' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Consolidate i.MX 5 platforms to be under the new shared i.MX 3/5/6 tree.
* tag 'arm-soc-imx-move' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM i.MX: Update defconfig
ARM i.MX: Merge i.MX5 support into mach-imx
ARM i.MX5: remove unnecessary includes from board files
Fix up fairly trivial conflicts due to various changes nearby in
arch/arm/{mach,plat}-imx/{Kconfig,Makefile}
Pull request had been sent to the wrong email address, but happened
before the merge window closed. I'm merging the MX 5 consolidation,
since it apparently will help the next development window and will avoid
conflicts later as per Arnd.
226 lines
5.7 KiB
C
226 lines
5.7 KiB
C
/*
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* Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <mach/common.h>
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#include <mach/hardware.h>
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#include <mach/iomux-mx50.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/time.h>
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#include "devices-imx50.h"
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#define FEC_EN IMX_GPIO_NR(6, 23)
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#define FEC_RESET_B IMX_GPIO_NR(4, 12)
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static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
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/* SD1 */
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MX50_PAD_ECSPI2_SS0__GPIO_4_19,
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MX50_PAD_EIM_CRE__GPIO_1_27,
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MX50_PAD_SD1_CMD__SD1_CMD,
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MX50_PAD_SD1_CLK__SD1_CLK,
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MX50_PAD_SD1_D0__SD1_D0,
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MX50_PAD_SD1_D1__SD1_D1,
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MX50_PAD_SD1_D2__SD1_D2,
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MX50_PAD_SD1_D3__SD1_D3,
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/* SD2 */
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MX50_PAD_SD2_CD__GPIO_5_17,
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MX50_PAD_SD2_WP__GPIO_5_16,
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MX50_PAD_SD2_CMD__SD2_CMD,
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MX50_PAD_SD2_CLK__SD2_CLK,
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MX50_PAD_SD2_D0__SD2_D0,
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MX50_PAD_SD2_D1__SD2_D1,
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MX50_PAD_SD2_D2__SD2_D2,
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MX50_PAD_SD2_D3__SD2_D3,
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MX50_PAD_SD2_D4__SD2_D4,
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MX50_PAD_SD2_D5__SD2_D5,
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MX50_PAD_SD2_D6__SD2_D6,
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MX50_PAD_SD2_D7__SD2_D7,
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/* SD3 */
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MX50_PAD_SD3_CMD__SD3_CMD,
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MX50_PAD_SD3_CLK__SD3_CLK,
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MX50_PAD_SD3_D0__SD3_D0,
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MX50_PAD_SD3_D1__SD3_D1,
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MX50_PAD_SD3_D2__SD3_D2,
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MX50_PAD_SD3_D3__SD3_D3,
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MX50_PAD_SD3_D4__SD3_D4,
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MX50_PAD_SD3_D5__SD3_D5,
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MX50_PAD_SD3_D6__SD3_D6,
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MX50_PAD_SD3_D7__SD3_D7,
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/* PWR_INT */
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MX50_PAD_ECSPI2_MISO__GPIO_4_18,
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/* UART pad setting */
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MX50_PAD_UART1_TXD__UART1_TXD,
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MX50_PAD_UART1_RXD__UART1_RXD,
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MX50_PAD_UART1_RTS__UART1_RTS,
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MX50_PAD_UART2_TXD__UART2_TXD,
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MX50_PAD_UART2_RXD__UART2_RXD,
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MX50_PAD_UART2_CTS__UART2_CTS,
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MX50_PAD_UART2_RTS__UART2_RTS,
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MX50_PAD_I2C1_SCL__I2C1_SCL,
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MX50_PAD_I2C1_SDA__I2C1_SDA,
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MX50_PAD_I2C2_SCL__I2C2_SCL,
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MX50_PAD_I2C2_SDA__I2C2_SDA,
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MX50_PAD_EPITO__USBH1_PWR,
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/* Need to comment below line if
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* one needs to debug owire.
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*/
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MX50_PAD_OWIRE__USBH1_OC,
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/* using gpio to control otg pwr */
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MX50_PAD_PWM2__GPIO_6_25,
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MX50_PAD_I2C3_SCL__USBOTG_OC,
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MX50_PAD_SSI_RXC__FEC_MDIO,
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MX50_PAD_SSI_RXFS__FEC_MDC,
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MX50_PAD_DISP_D0__FEC_TXCLK,
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MX50_PAD_DISP_D1__FEC_RX_ER,
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MX50_PAD_DISP_D2__FEC_RX_DV,
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MX50_PAD_DISP_D3__FEC_RXD1,
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MX50_PAD_DISP_D4__FEC_RXD0,
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MX50_PAD_DISP_D5__FEC_TX_EN,
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MX50_PAD_DISP_D6__FEC_TXD1,
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MX50_PAD_DISP_D7__FEC_TXD0,
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MX50_PAD_I2C3_SDA__GPIO_6_23,
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MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
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MX50_PAD_CSPI_SS0__CSPI_SS0,
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MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
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MX50_PAD_CSPI_MOSI__CSPI_MOSI,
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MX50_PAD_CSPI_MISO__CSPI_MISO,
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/* SGTL500_OSC_EN */
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MX50_PAD_UART1_CTS__GPIO_6_8,
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/* SGTL_AMP_SHDN */
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MX50_PAD_UART3_RXD__GPIO_6_15,
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/* Keypad */
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MX50_PAD_KEY_COL0__KEY_COL0,
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MX50_PAD_KEY_ROW0__KEY_ROW0,
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MX50_PAD_KEY_COL1__KEY_COL1,
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MX50_PAD_KEY_ROW1__KEY_ROW1,
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MX50_PAD_KEY_COL2__KEY_COL2,
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MX50_PAD_KEY_ROW2__KEY_ROW2,
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MX50_PAD_KEY_COL3__KEY_COL3,
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MX50_PAD_KEY_ROW3__KEY_ROW3,
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MX50_PAD_EIM_DA0__KEY_COL4,
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MX50_PAD_EIM_DA1__KEY_ROW4,
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MX50_PAD_EIM_DA2__KEY_COL5,
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MX50_PAD_EIM_DA3__KEY_ROW5,
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MX50_PAD_EIM_DA4__KEY_COL6,
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MX50_PAD_EIM_DA5__KEY_ROW6,
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MX50_PAD_EIM_DA6__KEY_COL7,
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MX50_PAD_EIM_DA7__KEY_ROW7,
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/*EIM pads */
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MX50_PAD_EIM_DA8__GPIO_1_8,
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MX50_PAD_EIM_DA9__GPIO_1_9,
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MX50_PAD_EIM_DA10__GPIO_1_10,
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MX50_PAD_EIM_DA11__GPIO_1_11,
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MX50_PAD_EIM_DA12__GPIO_1_12,
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MX50_PAD_EIM_DA13__GPIO_1_13,
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MX50_PAD_EIM_DA14__GPIO_1_14,
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MX50_PAD_EIM_DA15__GPIO_1_15,
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MX50_PAD_EIM_CS2__GPIO_1_16,
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MX50_PAD_EIM_CS1__GPIO_1_17,
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MX50_PAD_EIM_CS0__GPIO_1_18,
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MX50_PAD_EIM_EB0__GPIO_1_19,
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MX50_PAD_EIM_EB1__GPIO_1_20,
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MX50_PAD_EIM_WAIT__GPIO_1_21,
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MX50_PAD_EIM_BCLK__GPIO_1_22,
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MX50_PAD_EIM_RDY__GPIO_1_23,
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MX50_PAD_EIM_OE__GPIO_1_24,
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};
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/* Serial ports */
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static const struct imxuart_platform_data uart_pdata __initconst = {
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.flags = IMXUART_HAVE_RTSCTS,
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};
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static const struct fec_platform_data fec_data __initconst = {
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.phy = PHY_INTERFACE_MODE_RMII,
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};
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static inline void mx50_rdp_fec_reset(void)
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{
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gpio_request(FEC_EN, "fec-en");
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gpio_direction_output(FEC_EN, 0);
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gpio_request(FEC_RESET_B, "fec-reset_b");
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gpio_direction_output(FEC_RESET_B, 0);
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msleep(1);
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gpio_set_value(FEC_RESET_B, 1);
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}
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static const struct imxi2c_platform_data i2c_data __initconst = {
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.bitrate = 100000,
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};
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/*
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* Board specific initialization.
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*/
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static void __init mx50_rdp_board_init(void)
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{
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imx50_soc_init();
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mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
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ARRAY_SIZE(mx50_rdp_pads));
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imx50_add_imx_uart(0, &uart_pdata);
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imx50_add_imx_uart(1, &uart_pdata);
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mx50_rdp_fec_reset();
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imx50_add_fec(&fec_data);
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imx50_add_imx_i2c(0, &i2c_data);
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imx50_add_imx_i2c(1, &i2c_data);
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imx50_add_imx_i2c(2, &i2c_data);
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}
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static void __init mx50_rdp_timer_init(void)
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{
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mx50_clocks_init(32768, 24000000, 22579200);
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}
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static struct sys_timer mx50_rdp_timer = {
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.init = mx50_rdp_timer_init,
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};
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MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
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.map_io = mx50_map_io,
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.init_early = imx50_init_early,
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.init_irq = mx50_init_irq,
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.handle_irq = imx50_handle_irq,
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.timer = &mx50_rdp_timer,
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.init_machine = mx50_rdp_board_init,
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.restart = mxc_restart,
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MACHINE_END
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