269 lines
6.8 KiB
C
269 lines
6.8 KiB
C
/*
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* Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
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* reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the NetLogic
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <linux/interrupt.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#include <asm/errno.h>
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#include <asm/signal.h>
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#include <asm/ptrace.h>
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#include <asm/mipsregs.h>
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#include <asm/thread_info.h>
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#include <asm/netlogic/mips-extns.h>
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#include <asm/netlogic/interrupt.h>
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#include <asm/netlogic/haldefs.h>
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#include <asm/netlogic/common.h>
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#if defined(CONFIG_CPU_XLP)
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#include <asm/netlogic/xlp-hal/iomap.h>
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#include <asm/netlogic/xlp-hal/xlp.h>
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#include <asm/netlogic/xlp-hal/pic.h>
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#elif defined(CONFIG_CPU_XLR)
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#include <asm/netlogic/xlr/iomap.h>
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#include <asm/netlogic/xlr/pic.h>
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#include <asm/netlogic/xlr/fmn.h>
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#else
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#error "Unknown CPU"
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#endif
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#ifdef CONFIG_SMP
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#define SMP_IRQ_MASK ((1ULL << IRQ_IPI_SMP_FUNCTION) | \
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(1ULL << IRQ_IPI_SMP_RESCHEDULE))
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#else
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#define SMP_IRQ_MASK 0
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#endif
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#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \
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(1ull << IRQ_FMN))
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struct nlm_pic_irq {
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void (*extra_ack)(struct irq_data *);
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struct nlm_soc_info *node;
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int picirq;
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int irt;
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int flags;
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};
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static void xlp_pic_enable(struct irq_data *d)
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{
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unsigned long flags;
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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BUG_ON(!pd);
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spin_lock_irqsave(&pd->node->piclock, flags);
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nlm_pic_enable_irt(pd->node->picbase, pd->irt);
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spin_unlock_irqrestore(&pd->node->piclock, flags);
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}
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static void xlp_pic_disable(struct irq_data *d)
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{
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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unsigned long flags;
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BUG_ON(!pd);
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spin_lock_irqsave(&pd->node->piclock, flags);
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nlm_pic_disable_irt(pd->node->picbase, pd->irt);
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spin_unlock_irqrestore(&pd->node->piclock, flags);
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}
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static void xlp_pic_mask_ack(struct irq_data *d)
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{
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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clear_c0_eimr(pd->picirq);
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ack_c0_eirr(pd->picirq);
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}
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static void xlp_pic_unmask(struct irq_data *d)
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{
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struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
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BUG_ON(!pd);
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if (pd->extra_ack)
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pd->extra_ack(d);
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/* re-enable the intr on this cpu */
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set_c0_eimr(pd->picirq);
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/* Ack is a single write, no need to lock */
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nlm_pic_ack(pd->node->picbase, pd->irt);
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}
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static struct irq_chip xlp_pic = {
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.name = "XLP-PIC",
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.irq_enable = xlp_pic_enable,
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.irq_disable = xlp_pic_disable,
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.irq_mask_ack = xlp_pic_mask_ack,
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.irq_unmask = xlp_pic_unmask,
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};
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static void cpuintr_disable(struct irq_data *d)
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{
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clear_c0_eimr(d->irq);
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}
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static void cpuintr_enable(struct irq_data *d)
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{
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set_c0_eimr(d->irq);
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}
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static void cpuintr_ack(struct irq_data *d)
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{
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ack_c0_eirr(d->irq);
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}
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/*
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* Chip definition for CPU originated interrupts(timer, msg) and
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* IPIs
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*/
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struct irq_chip nlm_cpu_intr = {
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.name = "XLP-CPU-INTR",
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.irq_enable = cpuintr_enable,
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.irq_disable = cpuintr_disable,
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.irq_mask = cpuintr_disable,
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.irq_ack = cpuintr_ack,
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.irq_eoi = cpuintr_enable,
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};
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static void __init nlm_init_percpu_irqs(void)
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{
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int i;
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for (i = 0; i < PIC_IRT_FIRST_IRQ; i++)
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irq_set_chip_and_handler(i, &nlm_cpu_intr, handle_percpu_irq);
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#ifdef CONFIG_SMP
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irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
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nlm_smp_function_ipi_handler);
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irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
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nlm_smp_resched_ipi_handler);
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#endif
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}
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void nlm_setup_pic_irq(int node, int picirq, int irq, int irt)
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{
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struct nlm_pic_irq *pic_data;
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int xirq;
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xirq = nlm_irq_to_xirq(node, irq);
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pic_data = kzalloc(sizeof(*pic_data), GFP_KERNEL);
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BUG_ON(pic_data == NULL);
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pic_data->irt = irt;
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pic_data->picirq = picirq;
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pic_data->node = nlm_get_node(node);
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irq_set_chip_and_handler(xirq, &xlp_pic, handle_level_irq);
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irq_set_handler_data(xirq, pic_data);
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}
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void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *))
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{
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struct nlm_pic_irq *pic_data;
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int xirq;
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xirq = nlm_irq_to_xirq(node, irq);
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pic_data = irq_get_handler_data(xirq);
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pic_data->extra_ack = xack;
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}
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static void nlm_init_node_irqs(int node)
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{
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int i, irt;
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uint64_t irqmask;
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struct nlm_soc_info *nodep;
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pr_info("Init IRQ for node %d\n", node);
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nodep = nlm_get_node(node);
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irqmask = PERCPU_IRQ_MASK;
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for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++) {
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irt = nlm_irq_to_irt(i);
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if (irt == -1)
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continue;
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nlm_setup_pic_irq(node, i, i, irt);
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/* set interrupts to first cpu in node */
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nlm_pic_init_irt(nodep->picbase, irt, i,
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node * NLM_CPUS_PER_NODE, 0);
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irqmask |= (1ull << i);
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}
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nodep->irqmask = irqmask;
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}
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void __init arch_init_irq(void)
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{
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/* Initialize the irq descriptors */
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nlm_init_percpu_irqs();
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nlm_init_node_irqs(0);
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write_c0_eimr(nlm_current_node()->irqmask);
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#if defined(CONFIG_CPU_XLR)
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nlm_setup_fmn_irq();
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#endif
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}
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void nlm_smp_irq_init(int hwcpuid)
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{
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int node, cpu;
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node = hwcpuid / NLM_CPUS_PER_NODE;
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cpu = hwcpuid % NLM_CPUS_PER_NODE;
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if (cpu == 0 && node != 0)
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nlm_init_node_irqs(node);
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write_c0_eimr(nlm_current_node()->irqmask);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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uint64_t eirr;
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int i, node;
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node = nlm_nodeid();
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eirr = read_c0_eirr_and_eimr();
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i = __ilog2_u64(eirr);
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if (i == -1)
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return;
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/* per-CPU IRQs don't need translation */
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if (eirr & PERCPU_IRQ_MASK) {
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do_IRQ(i);
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return;
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}
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/* top level irq handling */
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do_IRQ(nlm_irq_to_xirq(node, i));
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}
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