 324808c2bc
			
		
	
	
	324808c2bc
	
	
	
		
			
			Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Chen Liqin <liqin.chen@sunplusct.com>
		
			
				
	
	
		
			111 lines
		
	
	
	
		
			2.9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			111 lines
		
	
	
	
		
			2.9 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * arch/score/kernel/irq.c
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|  *
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|  * Score Processor version.
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|  *
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|  * Copyright (C) 2009 Sunplus Core Technology Co., Ltd.
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|  *  Chen Liqin <liqin.chen@sunplusct.com>
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|  *  Lennox Wu <lennox.wu@sunplusct.com>
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; either version 2 of the License, or
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|  * (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, see the file COPYING, or write
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|  * to the Free Software Foundation, Inc.,
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|  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
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|  */
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| 
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| #include <linux/interrupt.h>
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| #include <linux/kernel_stat.h>
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| #include <linux/seq_file.h>
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| 
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| #include <asm/io.h>
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| 
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| /* the interrupt controller is hardcoded at this address */
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| #define SCORE_PIC		((u32 __iomem __force *)0x95F50000)
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| 
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| #define INT_PNDL		0
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| #define INT_PNDH		1
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| #define INT_PRIORITY_M		2
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| #define INT_PRIORITY_SG0	4
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| #define INT_PRIORITY_SG1	5
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| #define INT_PRIORITY_SG2	6
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| #define INT_PRIORITY_SG3	7
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| #define INT_MASKL		8
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| #define INT_MASKH		9
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| 
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| /*
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|  * handles all normal device IRQs
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|  */
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| asmlinkage void do_IRQ(int irq)
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| {
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| 	irq_enter();
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| 	generic_handle_irq(irq);
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| 	irq_exit();
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| }
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| 
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| static void score_mask(struct irq_data *d)
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| {
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| 	unsigned int irq_source = 63 - d->irq;
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| 
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| 	if (irq_source < 32)
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| 		__raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \
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| 			(1 << irq_source)), SCORE_PIC + INT_MASKL);
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| 	else
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| 		__raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) | \
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| 			(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
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| }
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| 
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| static void score_unmask(struct irq_data *d)
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| {
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| 	unsigned int irq_source = 63 - d->irq;
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| 
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| 	if (irq_source < 32)
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| 		__raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \
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| 			~(1 << irq_source)), SCORE_PIC + INT_MASKL);
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| 	else
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| 		__raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) & \
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| 			~(1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
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| }
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| 
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| struct irq_chip score_irq_chip = {
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| 	.name		= "Score7-level",
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| 	.irq_mask	= score_mask,
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| 	.irq_mask_ack	= score_mask,
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| 	.irq_unmask	= score_unmask,
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| };
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| 
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| /*
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|  * initialise the interrupt system
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|  */
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| void __init init_IRQ(void)
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| {
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| 	int index;
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| 	unsigned long target_addr;
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| 
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| 	for (index = 0; index < NR_IRQS; ++index)
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| 		irq_set_chip_and_handler(index, &score_irq_chip,
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| 					 handle_level_irq);
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| 
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| 	for (target_addr = IRQ_VECTOR_BASE_ADDR;
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| 		target_addr <= IRQ_VECTOR_END_ADDR;
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| 		target_addr += IRQ_VECTOR_SIZE)
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| 		memcpy((void *)target_addr, \
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| 			interrupt_exception_vector, IRQ_VECTOR_SIZE);
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| 
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| 	__raw_writel(0xffffffff, SCORE_PIC + INT_MASKL);
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| 	__raw_writel(0xffffffff, SCORE_PIC + INT_MASKH);
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| 
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| 	__asm__ __volatile__(
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| 		"mtcr	%0, cr3\n\t"
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| 		: : "r" (EXCEPTION_VECTOR_BASE_ADDR | \
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| 			VECTOR_ADDRESS_OFFSET_MODE16));
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| }
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