0ee958e102
This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
191 lines
3.7 KiB
ArmAsm
191 lines
3.7 KiB
ArmAsm
/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#define GCR_CL_COHERENCE_OFS 0x2008
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.section .text.cps-vec
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.balign 0x1000
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.set noreorder
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LEAF(mips_cps_core_entry)
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/*
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* These first 8 bytes will be patched by cps_smp_setup to load the
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* base address of the CM GCRs into register v1.
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*/
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.quad 0
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/* Check whether we're here due to an NMI */
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mfc0 k0, CP0_STATUS
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and k0, k0, ST0_NMI
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beqz k0, not_nmi
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nop
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/* This is an NMI */
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la k0, nmi_handler
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jr k0
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nop
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not_nmi:
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/* Setup Cause */
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li t0, CAUSEF_IV
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mtc0 t0, CP0_CAUSE
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/* Setup Status */
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li t0, ST0_CU1 | ST0_CU0
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mtc0 t0, CP0_STATUS
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/*
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* Clear the bits used to index the caches. Note that the architecture
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* dictates that writing to any of TagLo or TagHi selects 0 or 2 should
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* be valid for all MIPS32 CPUs, even those for which said writes are
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* unnecessary.
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*/
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mtc0 zero, CP0_TAGLO, 0
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mtc0 zero, CP0_TAGHI, 0
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mtc0 zero, CP0_TAGLO, 2
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mtc0 zero, CP0_TAGHI, 2
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ehb
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/* Primary cache configuration is indicated by Config1 */
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mfc0 v0, CP0_CONFIG, 1
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/* Detect I-cache line size */
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_EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
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beqz t0, icache_done
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li t1, 2
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sllv t0, t1, t0
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/* Detect I-cache size */
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_EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
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xori t2, t1, 0x7
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beqz t2, 1f
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li t3, 32
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addi t1, t1, 1
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sllv t1, t3, t1
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1: /* At this point t1 == I-cache sets per way */
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_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
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addi t2, t2, 1
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mul t1, t1, t0
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mul t1, t1, t2
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li a0, KSEG0
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add a1, a0, t1
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1: cache Index_Store_Tag_I, 0(a0)
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add a0, a0, t0
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bne a0, a1, 1b
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nop
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icache_done:
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/* Detect D-cache line size */
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_EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
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beqz t0, dcache_done
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li t1, 2
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sllv t0, t1, t0
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/* Detect D-cache size */
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_EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
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xori t2, t1, 0x7
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beqz t2, 1f
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li t3, 32
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addi t1, t1, 1
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sllv t1, t3, t1
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1: /* At this point t1 == D-cache sets per way */
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_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
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addi t2, t2, 1
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mul t1, t1, t0
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mul t1, t1, t2
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li a0, KSEG0
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addu a1, a0, t1
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subu a1, a1, t0
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1: cache Index_Store_Tag_D, 0(a0)
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bne a0, a1, 1b
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add a0, a0, t0
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dcache_done:
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/* Set Kseg0 cacheable, coherent, write-back, write-allocate */
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mfc0 t0, CP0_CONFIG
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ori t0, 0x7
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xori t0, 0x2
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mtc0 t0, CP0_CONFIG
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ehb
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/* Enter the coherent domain */
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li t0, 0xff
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sw t0, GCR_CL_COHERENCE_OFS(v1)
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ehb
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/* Jump to kseg0 */
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la t0, 1f
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jr t0
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nop
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1: /* We're up, cached & coherent */
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/*
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* TODO: We should check the VPE number we intended to boot here, and
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* if non-zero we should start that VPE and stop this one. For
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* the moment this doesn't matter since CPUs are brought up
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* sequentially and in order, but once hotplug is implemented
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* this will need revisiting.
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*/
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/* Off we go! */
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la t0, mips_cps_bootcfg
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lw t1, BOOTCFG_PC(t0)
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lw gp, BOOTCFG_GP(t0)
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lw sp, BOOTCFG_SP(t0)
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jr t1
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nop
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END(mips_cps_core_entry)
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.org 0x200
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LEAF(excep_tlbfill)
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b .
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nop
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END(excep_tlbfill)
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.org 0x280
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LEAF(excep_xtlbfill)
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b .
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nop
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END(excep_xtlbfill)
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.org 0x300
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LEAF(excep_cache)
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b .
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nop
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END(excep_cache)
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.org 0x380
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LEAF(excep_genex)
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b .
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nop
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END(excep_genex)
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.org 0x400
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LEAF(excep_intex)
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b .
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nop
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END(excep_intex)
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.org 0x480
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LEAF(excep_ejtag)
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la k0, ejtag_debug_handler
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jr k0
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nop
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END(excep_ejtag)
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