883c057367
Commit 64681787 (arm64: let the core code deal with preempt_count)
changed the code, but left the comments unchanged, fix it.
Signed-off-by: Neil Zhang <zhangwm@marvell.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
682 lines
15 KiB
ArmAsm
682 lines
15 KiB
ArmAsm
/*
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* Low-level exception handling code
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*
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* Copyright (C) 2012 ARM Ltd.
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* Authors: Catalin Marinas <catalin.marinas@arm.com>
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* Will Deacon <will.deacon@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/errno.h>
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#include <asm/esr.h>
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#include <asm/thread_info.h>
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#include <asm/unistd.h>
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#include <asm/unistd32.h>
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/*
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* Bad Abort numbers
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*-----------------
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*/
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#define BAD_SYNC 0
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#define BAD_IRQ 1
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#define BAD_FIQ 2
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#define BAD_ERROR 3
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.macro kernel_entry, el, regsize = 64
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sub sp, sp, #S_FRAME_SIZE - S_LR // room for LR, SP, SPSR, ELR
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.if \regsize == 32
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mov w0, w0 // zero upper 32 bits of x0
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.endif
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push x28, x29
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push x26, x27
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push x24, x25
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push x22, x23
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push x20, x21
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push x18, x19
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push x16, x17
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push x14, x15
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push x12, x13
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push x10, x11
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push x8, x9
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push x6, x7
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push x4, x5
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push x2, x3
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push x0, x1
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.if \el == 0
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mrs x21, sp_el0
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.else
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add x21, sp, #S_FRAME_SIZE
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.endif
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mrs x22, elr_el1
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mrs x23, spsr_el1
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stp lr, x21, [sp, #S_LR]
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stp x22, x23, [sp, #S_PC]
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/*
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* Set syscallno to -1 by default (overridden later if real syscall).
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*/
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.if \el == 0
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mvn x21, xzr
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str x21, [sp, #S_SYSCALLNO]
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.endif
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/*
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* Registers that may be useful after this macro is invoked:
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*
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* x21 - aborted SP
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* x22 - aborted PC
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* x23 - aborted PSTATE
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*/
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.endm
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.macro kernel_exit, el, ret = 0
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ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
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.if \el == 0
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ldr x23, [sp, #S_SP] // load return stack pointer
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.endif
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.if \ret
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ldr x1, [sp, #S_X1] // preserve x0 (syscall return)
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add sp, sp, S_X2
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.else
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pop x0, x1
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.endif
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pop x2, x3 // load the rest of the registers
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pop x4, x5
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pop x6, x7
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pop x8, x9
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msr elr_el1, x21 // set up the return data
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msr spsr_el1, x22
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.if \el == 0
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msr sp_el0, x23
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.endif
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pop x10, x11
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pop x12, x13
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pop x14, x15
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pop x16, x17
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pop x18, x19
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pop x20, x21
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pop x22, x23
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pop x24, x25
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pop x26, x27
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pop x28, x29
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ldr lr, [sp], #S_FRAME_SIZE - S_LR // load LR and restore SP
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eret // return to kernel
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.endm
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.macro get_thread_info, rd
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mov \rd, sp
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and \rd, \rd, #~(THREAD_SIZE - 1) // top of stack
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.endm
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/*
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* These are the registers used in the syscall handler, and allow us to
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* have in theory up to 7 arguments to a function - x0 to x6.
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*
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* x7 is reserved for the system call number in 32-bit mode.
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*/
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sc_nr .req x25 // number of system calls
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scno .req x26 // syscall number
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stbl .req x27 // syscall table pointer
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tsk .req x28 // current thread_info
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/*
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* Interrupt handling.
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*/
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.macro irq_handler
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ldr x1, handle_arch_irq
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mov x0, sp
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blr x1
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.endm
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.text
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/*
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* Exception vectors.
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*/
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.align 11
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ENTRY(vectors)
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ventry el1_sync_invalid // Synchronous EL1t
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ventry el1_irq_invalid // IRQ EL1t
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ventry el1_fiq_invalid // FIQ EL1t
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ventry el1_error_invalid // Error EL1t
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ventry el1_sync // Synchronous EL1h
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ventry el1_irq // IRQ EL1h
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ventry el1_fiq_invalid // FIQ EL1h
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ventry el1_error_invalid // Error EL1h
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ventry el0_sync // Synchronous 64-bit EL0
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ventry el0_irq // IRQ 64-bit EL0
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ventry el0_fiq_invalid // FIQ 64-bit EL0
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ventry el0_error_invalid // Error 64-bit EL0
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#ifdef CONFIG_COMPAT
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ventry el0_sync_compat // Synchronous 32-bit EL0
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ventry el0_irq_compat // IRQ 32-bit EL0
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ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
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ventry el0_error_invalid_compat // Error 32-bit EL0
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#else
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ventry el0_sync_invalid // Synchronous 32-bit EL0
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ventry el0_irq_invalid // IRQ 32-bit EL0
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ventry el0_fiq_invalid // FIQ 32-bit EL0
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ventry el0_error_invalid // Error 32-bit EL0
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#endif
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END(vectors)
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/*
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* Invalid mode handlers
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*/
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.macro inv_entry, el, reason, regsize = 64
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kernel_entry el, \regsize
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mov x0, sp
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mov x1, #\reason
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mrs x2, esr_el1
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b bad_mode
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.endm
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el0_sync_invalid:
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inv_entry 0, BAD_SYNC
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ENDPROC(el0_sync_invalid)
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el0_irq_invalid:
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inv_entry 0, BAD_IRQ
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ENDPROC(el0_irq_invalid)
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el0_fiq_invalid:
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inv_entry 0, BAD_FIQ
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ENDPROC(el0_fiq_invalid)
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el0_error_invalid:
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inv_entry 0, BAD_ERROR
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ENDPROC(el0_error_invalid)
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#ifdef CONFIG_COMPAT
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el0_fiq_invalid_compat:
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inv_entry 0, BAD_FIQ, 32
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ENDPROC(el0_fiq_invalid_compat)
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el0_error_invalid_compat:
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inv_entry 0, BAD_ERROR, 32
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ENDPROC(el0_error_invalid_compat)
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#endif
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el1_sync_invalid:
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inv_entry 1, BAD_SYNC
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ENDPROC(el1_sync_invalid)
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el1_irq_invalid:
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inv_entry 1, BAD_IRQ
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ENDPROC(el1_irq_invalid)
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el1_fiq_invalid:
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inv_entry 1, BAD_FIQ
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ENDPROC(el1_fiq_invalid)
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el1_error_invalid:
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inv_entry 1, BAD_ERROR
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ENDPROC(el1_error_invalid)
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/*
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* EL1 mode handlers.
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*/
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.align 6
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el1_sync:
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kernel_entry 1
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mrs x1, esr_el1 // read the syndrome register
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lsr x24, x1, #ESR_EL1_EC_SHIFT // exception class
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cmp x24, #ESR_EL1_EC_DABT_EL1 // data abort in EL1
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b.eq el1_da
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cmp x24, #ESR_EL1_EC_SYS64 // configurable trap
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b.eq el1_undef
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cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception
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b.eq el1_sp_pc
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cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception
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b.eq el1_sp_pc
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cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL1
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b.eq el1_undef
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cmp x24, #ESR_EL1_EC_BREAKPT_EL1 // debug exception in EL1
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b.ge el1_dbg
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b el1_inv
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el1_da:
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/*
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* Data abort handling
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*/
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mrs x0, far_el1
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enable_dbg_if_not_stepping x2
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// re-enable interrupts if they were enabled in the aborted context
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tbnz x23, #7, 1f // PSR_I_BIT
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enable_irq
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1:
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mov x2, sp // struct pt_regs
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bl do_mem_abort
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// disable interrupts before pulling preserved data off the stack
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disable_irq
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kernel_exit 1
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el1_sp_pc:
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/*
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* Stack or PC alignment exception handling
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*/
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mrs x0, far_el1
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mov x1, x25
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mov x2, sp
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b do_sp_pc_abort
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el1_undef:
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/*
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* Undefined instruction
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*/
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mov x0, sp
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b do_undefinstr
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el1_dbg:
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/*
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* Debug exception handling
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*/
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cmp x24, #ESR_EL1_EC_BRK64 // if BRK64
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cinc x24, x24, eq // set bit '0'
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tbz x24, #0, el1_inv // EL1 only
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mrs x0, far_el1
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mov x2, sp // struct pt_regs
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bl do_debug_exception
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kernel_exit 1
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el1_inv:
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// TODO: add support for undefined instructions in kernel mode
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mov x0, sp
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mov x1, #BAD_SYNC
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mrs x2, esr_el1
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b bad_mode
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ENDPROC(el1_sync)
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.align 6
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el1_irq:
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kernel_entry 1
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enable_dbg_if_not_stepping x0
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_off
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#endif
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irq_handler
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#ifdef CONFIG_PREEMPT
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get_thread_info tsk
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ldr w24, [tsk, #TI_PREEMPT] // get preempt count
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cbnz w24, 1f // preempt count != 0
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ldr x0, [tsk, #TI_FLAGS] // get flags
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tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
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bl el1_preempt
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1:
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#endif
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_on
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#endif
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kernel_exit 1
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ENDPROC(el1_irq)
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#ifdef CONFIG_PREEMPT
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el1_preempt:
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mov x24, lr
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1: enable_dbg
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bl preempt_schedule_irq // irq en/disable is done inside
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ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
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tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
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ret x24
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#endif
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/*
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* EL0 mode handlers.
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*/
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.align 6
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el0_sync:
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kernel_entry 0
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mrs x25, esr_el1 // read the syndrome register
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lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
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cmp x24, #ESR_EL1_EC_SVC64 // SVC in 64-bit state
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b.eq el0_svc
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adr lr, ret_from_exception
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cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
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b.eq el0_da
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cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
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b.eq el0_ia
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cmp x24, #ESR_EL1_EC_FP_ASIMD // FP/ASIMD access
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b.eq el0_fpsimd_acc
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cmp x24, #ESR_EL1_EC_FP_EXC64 // FP/ASIMD exception
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b.eq el0_fpsimd_exc
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cmp x24, #ESR_EL1_EC_SYS64 // configurable trap
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b.eq el0_undef
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cmp x24, #ESR_EL1_EC_SP_ALIGN // stack alignment exception
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b.eq el0_sp_pc
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cmp x24, #ESR_EL1_EC_PC_ALIGN // pc alignment exception
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b.eq el0_sp_pc
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cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0
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b.eq el0_undef
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cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
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b.ge el0_dbg
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b el0_inv
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#ifdef CONFIG_COMPAT
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.align 6
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el0_sync_compat:
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kernel_entry 0, 32
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mrs x25, esr_el1 // read the syndrome register
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lsr x24, x25, #ESR_EL1_EC_SHIFT // exception class
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cmp x24, #ESR_EL1_EC_SVC32 // SVC in 32-bit state
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b.eq el0_svc_compat
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adr lr, ret_from_exception
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cmp x24, #ESR_EL1_EC_DABT_EL0 // data abort in EL0
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b.eq el0_da
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cmp x24, #ESR_EL1_EC_IABT_EL0 // instruction abort in EL0
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b.eq el0_ia
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cmp x24, #ESR_EL1_EC_FP_ASIMD // FP/ASIMD access
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b.eq el0_fpsimd_acc
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cmp x24, #ESR_EL1_EC_FP_EXC32 // FP/ASIMD exception
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b.eq el0_fpsimd_exc
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cmp x24, #ESR_EL1_EC_UNKNOWN // unknown exception in EL0
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b.eq el0_undef
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cmp x24, #ESR_EL1_EC_CP15_32 // CP15 MRC/MCR trap
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b.eq el0_undef
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cmp x24, #ESR_EL1_EC_CP15_64 // CP15 MRRC/MCRR trap
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b.eq el0_undef
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cmp x24, #ESR_EL1_EC_CP14_MR // CP14 MRC/MCR trap
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b.eq el0_undef
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cmp x24, #ESR_EL1_EC_CP14_LS // CP14 LDC/STC trap
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b.eq el0_undef
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cmp x24, #ESR_EL1_EC_CP14_64 // CP14 MRRC/MCRR trap
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b.eq el0_undef
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cmp x24, #ESR_EL1_EC_BREAKPT_EL0 // debug exception in EL0
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b.ge el0_dbg
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b el0_inv
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el0_svc_compat:
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/*
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* AArch32 syscall handling
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*/
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adr stbl, compat_sys_call_table // load compat syscall table pointer
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uxtw scno, w7 // syscall number in w7 (r7)
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mov sc_nr, #__NR_compat_syscalls
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b el0_svc_naked
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.align 6
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el0_irq_compat:
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kernel_entry 0, 32
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b el0_irq_naked
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#endif
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el0_da:
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/*
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* Data abort handling
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*/
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mrs x0, far_el1
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bic x0, x0, #(0xff << 56)
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disable_step x1
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isb
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enable_dbg
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// enable interrupts before calling the main handler
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enable_irq
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mov x1, x25
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mov x2, sp
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b do_mem_abort
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el0_ia:
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/*
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* Instruction abort handling
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*/
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mrs x0, far_el1
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disable_step x1
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isb
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enable_dbg
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// enable interrupts before calling the main handler
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enable_irq
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orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts
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mov x2, sp
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b do_mem_abort
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el0_fpsimd_acc:
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/*
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* Floating Point or Advanced SIMD access
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*/
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mov x0, x25
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mov x1, sp
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b do_fpsimd_acc
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el0_fpsimd_exc:
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/*
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* Floating Point or Advanced SIMD exception
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*/
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mov x0, x25
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mov x1, sp
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b do_fpsimd_exc
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el0_sp_pc:
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/*
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* Stack or PC alignment exception handling
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*/
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mrs x0, far_el1
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disable_step x1
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isb
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enable_dbg
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// enable interrupts before calling the main handler
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enable_irq
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mov x1, x25
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mov x2, sp
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b do_sp_pc_abort
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el0_undef:
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/*
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* Undefined instruction
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*/
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mov x0, sp
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// enable interrupts before calling the main handler
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enable_irq
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b do_undefinstr
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el0_dbg:
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/*
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* Debug exception handling
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*/
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tbnz x24, #0, el0_inv // EL0 only
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mrs x0, far_el1
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disable_step x1
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mov x1, x25
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mov x2, sp
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b do_debug_exception
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el0_inv:
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mov x0, sp
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mov x1, #BAD_SYNC
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mrs x2, esr_el1
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b bad_mode
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ENDPROC(el0_sync)
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.align 6
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el0_irq:
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kernel_entry 0
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el0_irq_naked:
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disable_step x1
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isb
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enable_dbg
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_off
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#endif
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irq_handler
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get_thread_info tsk
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#ifdef CONFIG_TRACE_IRQFLAGS
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bl trace_hardirqs_on
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#endif
|
|
b ret_to_user
|
|
ENDPROC(el0_irq)
|
|
|
|
/*
|
|
* This is the return code to user mode for abort handlers
|
|
*/
|
|
ret_from_exception:
|
|
get_thread_info tsk
|
|
b ret_to_user
|
|
ENDPROC(ret_from_exception)
|
|
|
|
/*
|
|
* Register switch for AArch64. The callee-saved registers need to be saved
|
|
* and restored. On entry:
|
|
* x0 = previous task_struct (must be preserved across the switch)
|
|
* x1 = next task_struct
|
|
* Previous and next are guaranteed not to be the same.
|
|
*
|
|
*/
|
|
ENTRY(cpu_switch_to)
|
|
add x8, x0, #THREAD_CPU_CONTEXT
|
|
mov x9, sp
|
|
stp x19, x20, [x8], #16 // store callee-saved registers
|
|
stp x21, x22, [x8], #16
|
|
stp x23, x24, [x8], #16
|
|
stp x25, x26, [x8], #16
|
|
stp x27, x28, [x8], #16
|
|
stp x29, x9, [x8], #16
|
|
str lr, [x8]
|
|
add x8, x1, #THREAD_CPU_CONTEXT
|
|
ldp x19, x20, [x8], #16 // restore callee-saved registers
|
|
ldp x21, x22, [x8], #16
|
|
ldp x23, x24, [x8], #16
|
|
ldp x25, x26, [x8], #16
|
|
ldp x27, x28, [x8], #16
|
|
ldp x29, x9, [x8], #16
|
|
ldr lr, [x8]
|
|
mov sp, x9
|
|
ret
|
|
ENDPROC(cpu_switch_to)
|
|
|
|
/*
|
|
* This is the fast syscall return path. We do as little as possible here,
|
|
* and this includes saving x0 back into the kernel stack.
|
|
*/
|
|
ret_fast_syscall:
|
|
disable_irq // disable interrupts
|
|
ldr x1, [tsk, #TI_FLAGS]
|
|
and x2, x1, #_TIF_WORK_MASK
|
|
cbnz x2, fast_work_pending
|
|
tbz x1, #TIF_SINGLESTEP, fast_exit
|
|
disable_dbg
|
|
enable_step x2
|
|
fast_exit:
|
|
kernel_exit 0, ret = 1
|
|
|
|
/*
|
|
* Ok, we need to do extra processing, enter the slow path.
|
|
*/
|
|
fast_work_pending:
|
|
str x0, [sp, #S_X0] // returned x0
|
|
work_pending:
|
|
tbnz x1, #TIF_NEED_RESCHED, work_resched
|
|
/* TIF_SIGPENDING or TIF_NOTIFY_RESUME case */
|
|
ldr x2, [sp, #S_PSTATE]
|
|
mov x0, sp // 'regs'
|
|
tst x2, #PSR_MODE_MASK // user mode regs?
|
|
b.ne no_work_pending // returning to kernel
|
|
enable_irq // enable interrupts for do_notify_resume()
|
|
bl do_notify_resume
|
|
b ret_to_user
|
|
work_resched:
|
|
enable_dbg
|
|
bl schedule
|
|
|
|
/*
|
|
* "slow" syscall return path.
|
|
*/
|
|
ret_to_user:
|
|
disable_irq // disable interrupts
|
|
ldr x1, [tsk, #TI_FLAGS]
|
|
and x2, x1, #_TIF_WORK_MASK
|
|
cbnz x2, work_pending
|
|
tbz x1, #TIF_SINGLESTEP, no_work_pending
|
|
disable_dbg
|
|
enable_step x2
|
|
no_work_pending:
|
|
kernel_exit 0, ret = 0
|
|
ENDPROC(ret_to_user)
|
|
|
|
/*
|
|
* This is how we return from a fork.
|
|
*/
|
|
ENTRY(ret_from_fork)
|
|
bl schedule_tail
|
|
cbz x19, 1f // not a kernel thread
|
|
mov x0, x20
|
|
blr x19
|
|
1: get_thread_info tsk
|
|
b ret_to_user
|
|
ENDPROC(ret_from_fork)
|
|
|
|
/*
|
|
* SVC handler.
|
|
*/
|
|
.align 6
|
|
el0_svc:
|
|
adrp stbl, sys_call_table // load syscall table pointer
|
|
uxtw scno, w8 // syscall number in w8
|
|
mov sc_nr, #__NR_syscalls
|
|
el0_svc_naked: // compat entry point
|
|
stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
|
|
disable_step x16
|
|
isb
|
|
enable_dbg
|
|
enable_irq
|
|
|
|
get_thread_info tsk
|
|
ldr x16, [tsk, #TI_FLAGS] // check for syscall tracing
|
|
tbnz x16, #TIF_SYSCALL_TRACE, __sys_trace // are we tracing syscalls?
|
|
adr lr, ret_fast_syscall // return address
|
|
cmp scno, sc_nr // check upper syscall limit
|
|
b.hs ni_sys
|
|
ldr x16, [stbl, scno, lsl #3] // address in the syscall table
|
|
br x16 // call sys_* routine
|
|
ni_sys:
|
|
mov x0, sp
|
|
b do_ni_syscall
|
|
ENDPROC(el0_svc)
|
|
|
|
/*
|
|
* This is the really slow path. We're going to be doing context
|
|
* switches, and waiting for our parent to respond.
|
|
*/
|
|
__sys_trace:
|
|
mov x1, sp
|
|
mov w0, #0 // trace entry
|
|
bl syscall_trace
|
|
adr lr, __sys_trace_return // return address
|
|
uxtw scno, w0 // syscall number (possibly new)
|
|
mov x1, sp // pointer to regs
|
|
cmp scno, sc_nr // check upper syscall limit
|
|
b.hs ni_sys
|
|
ldp x0, x1, [sp] // restore the syscall args
|
|
ldp x2, x3, [sp, #S_X2]
|
|
ldp x4, x5, [sp, #S_X4]
|
|
ldp x6, x7, [sp, #S_X6]
|
|
ldr x16, [stbl, scno, lsl #3] // address in the syscall table
|
|
br x16 // call sys_* routine
|
|
|
|
__sys_trace_return:
|
|
str x0, [sp] // save returned x0
|
|
mov x1, sp
|
|
mov w0, #1 // trace exit
|
|
bl syscall_trace
|
|
b ret_to_user
|
|
|
|
/*
|
|
* Special system call wrappers.
|
|
*/
|
|
ENTRY(sys_rt_sigreturn_wrapper)
|
|
mov x0, sp
|
|
b sys_rt_sigreturn
|
|
ENDPROC(sys_rt_sigreturn_wrapper)
|
|
|
|
ENTRY(handle_arch_irq)
|
|
.quad 0
|