5f9403db5b
To facilitate upcoming cleanup in twl stack. No functional change. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
314 lines
8.9 KiB
C
314 lines
8.9 KiB
C
/**
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* OMAP and TWL PMIC specific intializations.
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*
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* Copyright (C) 2010 Texas Instruments Incorporated.
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* Thara Gopinath
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* Copyright (C) 2009 Texas Instruments Incorporated.
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* Nishanth Menon
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* Copyright (C) 2009 Nokia Corporation
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/i2c/twl.h>
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#include "soc.h"
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#include "voltage.h"
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#include "pm.h"
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#define OMAP3_SRI2C_SLAVE_ADDR 0x12
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#define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00
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#define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01
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#define OMAP3_VP_CONFIG_ERROROFFSET 0x00
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#define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1
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#define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
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#define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
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#define OMAP4_SRI2C_SLAVE_ADDR 0x12
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#define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
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#define OMAP4_VDD_MPU_SR_CMD_REG 0x56
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#define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B
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#define OMAP4_VDD_IVA_SR_CMD_REG 0x5C
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#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
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#define OMAP4_VDD_CORE_SR_CMD_REG 0x62
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#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
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#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
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#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
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#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
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static bool is_offset_valid;
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static u8 smps_offset;
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/*
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* Flag to ensure Smartreflex bit in TWL
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* being cleared in board file is not overwritten.
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*/
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static bool __initdata twl_sr_enable_autoinit;
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#define TWL4030_DCDC_GLOBAL_CFG 0x06
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#define REG_SMPS_OFFSET 0xE0
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#define SMARTREFLEX_ENABLE BIT(3)
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static unsigned long twl4030_vsel_to_uv(const u8 vsel)
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{
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return (((vsel * 125) + 6000)) * 100;
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}
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static u8 twl4030_uv_to_vsel(unsigned long uv)
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{
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return DIV_ROUND_UP(uv - 600000, 12500);
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}
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static unsigned long twl6030_vsel_to_uv(const u8 vsel)
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{
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/*
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* In TWL6030 depending on the value of SMPS_OFFSET
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* efuse register the voltage range supported in
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* standard mode can be either between 0.6V - 1.3V or
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* 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
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* is programmed to all 0's where as starting from
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* TWL6030 ES1.1 the efuse is programmed to 1
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*/
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if (!is_offset_valid) {
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twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
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REG_SMPS_OFFSET);
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is_offset_valid = true;
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}
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if (!vsel)
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return 0;
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/*
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* There is no specific formula for voltage to vsel
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* conversion above 1.3V. There are special hardcoded
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* values for voltages above 1.3V. Currently we are
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* hardcoding only for 1.35 V which is used for 1GH OPP for
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* OMAP4430.
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*/
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if (vsel == 0x3A)
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return 1350000;
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if (smps_offset & 0x8)
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return ((((vsel - 1) * 1266) + 70900)) * 10;
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else
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return ((((vsel - 1) * 1266) + 60770)) * 10;
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}
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static u8 twl6030_uv_to_vsel(unsigned long uv)
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{
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/*
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* In TWL6030 depending on the value of SMPS_OFFSET
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* efuse register the voltage range supported in
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* standard mode can be either between 0.6V - 1.3V or
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* 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
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* is programmed to all 0's where as starting from
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* TWL6030 ES1.1 the efuse is programmed to 1
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*/
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if (!is_offset_valid) {
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twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
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REG_SMPS_OFFSET);
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is_offset_valid = true;
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}
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if (!uv)
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return 0x00;
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/*
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* There is no specific formula for voltage to vsel
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* conversion above 1.3V. There are special hardcoded
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* values for voltages above 1.3V. Currently we are
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* hardcoding only for 1.35 V which is used for 1GH OPP for
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* OMAP4430.
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*/
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if (uv > twl6030_vsel_to_uv(0x39)) {
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if (uv == 1350000)
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return 0x3A;
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pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
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__func__, uv, twl6030_vsel_to_uv(0x39));
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return 0x3A;
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}
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if (smps_offset & 0x8)
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return DIV_ROUND_UP(uv - 709000, 12660) + 1;
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else
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return DIV_ROUND_UP(uv - 607700, 12660) + 1;
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}
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static struct omap_voltdm_pmic omap3_mpu_pmic = {
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.slew_rate = 4000,
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.step_size = 12500,
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.vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
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.vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
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.vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
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.vddmin = 600000,
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.vddmax = 1450000,
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.vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
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.i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
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.volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
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.i2c_high_speed = true,
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.vsel_to_uv = twl4030_vsel_to_uv,
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.uv_to_vsel = twl4030_uv_to_vsel,
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};
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static struct omap_voltdm_pmic omap3_core_pmic = {
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.slew_rate = 4000,
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.step_size = 12500,
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.vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
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.vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
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.vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
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.vddmin = 600000,
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.vddmax = 1450000,
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.vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
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.i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
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.volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
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.i2c_high_speed = true,
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.vsel_to_uv = twl4030_vsel_to_uv,
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.uv_to_vsel = twl4030_uv_to_vsel,
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};
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static struct omap_voltdm_pmic omap4_mpu_pmic = {
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.slew_rate = 4000,
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.step_size = 12660,
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.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
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.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
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.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
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.vddmin = 0,
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.vddmax = 2100000,
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.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
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.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
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.volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
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.cmd_reg_addr = OMAP4_VDD_MPU_SR_CMD_REG,
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.i2c_high_speed = true,
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.i2c_pad_load = 3,
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.vsel_to_uv = twl6030_vsel_to_uv,
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.uv_to_vsel = twl6030_uv_to_vsel,
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};
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static struct omap_voltdm_pmic omap4_iva_pmic = {
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.slew_rate = 4000,
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.step_size = 12660,
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.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
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.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
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.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
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.vddmin = 0,
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.vddmax = 2100000,
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.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
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.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
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.volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
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.cmd_reg_addr = OMAP4_VDD_IVA_SR_CMD_REG,
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.i2c_high_speed = true,
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.i2c_pad_load = 3,
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.vsel_to_uv = twl6030_vsel_to_uv,
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.uv_to_vsel = twl6030_uv_to_vsel,
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};
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static struct omap_voltdm_pmic omap4_core_pmic = {
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.slew_rate = 4000,
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.step_size = 12660,
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.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
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.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
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.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
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.vddmin = 0,
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.vddmax = 2100000,
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.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
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.i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
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.volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
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.cmd_reg_addr = OMAP4_VDD_CORE_SR_CMD_REG,
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.i2c_high_speed = true,
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.i2c_pad_load = 3,
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.vsel_to_uv = twl6030_vsel_to_uv,
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.uv_to_vsel = twl6030_uv_to_vsel,
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};
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int __init omap4_twl_init(void)
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{
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struct voltagedomain *voltdm;
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if (!cpu_is_omap44xx())
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return -ENODEV;
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voltdm = voltdm_lookup("mpu");
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omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
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voltdm = voltdm_lookup("iva");
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omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
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voltdm = voltdm_lookup("core");
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omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
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return 0;
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}
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int __init omap3_twl_init(void)
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{
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struct voltagedomain *voltdm;
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if (!cpu_is_omap34xx())
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return -ENODEV;
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/*
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* The smartreflex bit on twl4030 specifies if the setting of voltage
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* is done over the I2C_SR path. Since this setting is independent of
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* the actual usage of smartreflex AVS module, we enable TWL SR bit
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* by default irrespective of whether smartreflex AVS module is enabled
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* on the OMAP side or not. This is because without this bit enabled,
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* the voltage scaling through vp forceupdate/bypass mechanism of
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* voltage scaling will not function on TWL over I2C_SR.
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*/
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if (!twl_sr_enable_autoinit)
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omap3_twl_set_sr_bit(true);
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voltdm = voltdm_lookup("mpu_iva");
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omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
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voltdm = voltdm_lookup("core");
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omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
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return 0;
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}
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/**
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* omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
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* @enable: enable SR mode in twl or not
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*
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* If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
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* voltage scaling through OMAP SR works. Else, the smartreflex bit
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* on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
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* use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
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* Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
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* in those scenarios this bit is to be cleared (enable = false).
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*
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* Returns 0 on success, error is returned if I2C read/write fails.
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*/
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int __init omap3_twl_set_sr_bit(bool enable)
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{
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u8 temp;
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int ret;
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if (twl_sr_enable_autoinit)
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pr_warning("%s: unexpected multiple calls\n", __func__);
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ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
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TWL4030_DCDC_GLOBAL_CFG);
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if (ret)
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goto err;
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if (enable)
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temp |= SMARTREFLEX_ENABLE;
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else
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temp &= ~SMARTREFLEX_ENABLE;
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ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
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TWL4030_DCDC_GLOBAL_CFG);
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if (!ret) {
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twl_sr_enable_autoinit = true;
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return 0;
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}
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err:
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pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
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return ret;
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}
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