 a3a9384a11
			
		
	
	
	a3a9384a11
	
	
	
		
			
			The IO descriptor tables for DRA7 are a complete reuse from OMAP5. A new dra7xx_init_early() does the base address inits. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
		
			
				
	
	
		
			37 lines
		
	
	
	
		
			1.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			37 lines
		
	
	
	
		
			1.2 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*:
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|  * Address mappings and base address for OMAP5 interconnects
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|  * and peripherals.
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|  *
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|  * Copyright (C) 2012 Texas Instruments
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|  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
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|  *	Sricharan <r.sricharan@ti.com>
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License version 2 as
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|  * published by the Free Software Foundation.
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|  */
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| #ifndef __ASM_SOC_OMAP54XX_H
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| #define __ASM_SOC_OMAP54XX_H
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| 
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| /*
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|  * Please place only base defines here and put the rest in device
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|  * specific headers.
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|  */
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| #define L4_54XX_BASE			0x4a000000
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| #define L4_WK_54XX_BASE			0x4ae00000
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| #define L4_PER_54XX_BASE		0x48000000
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| #define L3_54XX_BASE			0x44000000
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| #define OMAP54XX_32KSYNCT_BASE		0x4ae04000
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| #define OMAP54XX_CM_CORE_AON_BASE	0x4a004000
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| #define OMAP54XX_CM_CORE_BASE		0x4a008000
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| #define OMAP54XX_PRM_BASE		0x4ae06000
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| #define OMAP54XX_PRCM_MPU_BASE		0x48243000
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| #define OMAP54XX_SCM_BASE		0x4a002000
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| #define OMAP54XX_CTRL_BASE		0x4a002800
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| #define OMAP54XX_SAR_RAM_BASE		0x4ae26000
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| 
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| #define DRA7XX_CM_CORE_AON_BASE		0x4a005000
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| #define DRA7XX_CTRL_BASE		0x4a003400
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| #define DRA7XX_TAP_BASE			0x4ae0c000
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| 
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| #endif /* __ASM_SOC_OMAP555554XX_H */
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