2f8b6fe4a9
There are no users of this API anymore so let's just remove it. If a need arises in the future we can extend the common clock API to handle it. Acked-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org>
31 lines
1 KiB
C
31 lines
1 KiB
C
/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __MACH_CLK_H
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#define __MACH_CLK_H
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/* Magic rate value for use with PM QOS to request the board's maximum
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* supported AXI rate. PM QOS will only pass positive s32 rate values
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* through to the clock driver, so INT_MAX is used.
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*/
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#define MSM_AXI_MAX_FREQ LONG_MAX
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enum clk_reset_action {
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CLK_RESET_DEASSERT = 0,
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CLK_RESET_ASSERT = 1
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};
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struct clk;
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/* Assert/Deassert reset to a hardware block associated with a clock */
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int clk_reset(struct clk *clk, enum clk_reset_action action);
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#endif
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