 97b09da4ee
			
		
	
	
	97b09da4ee
	
	
	
		
			
			This tries to clear up the confusion between integers and iomem pointers in the marvell pxa platform. MMIO addresses are supposed to be __iomem* values, in order to let the Linux type checking work correctly. This patch moves the cast to __iomem as far back as possible, to the place where the MMIO virtual address windows are defined. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
		
			
				
	
	
		
			71 lines
		
	
	
	
		
			1.7 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			71 lines
		
	
	
	
		
			1.7 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  *  linux/arch/arm/mach-mmp/clock.h
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|  *
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|  *  This program is free software; you can redistribute it and/or modify
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|  *  it under the terms of the GNU General Public License version 2 as
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|  *  published by the Free Software Foundation.
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|  */
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| 
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| #include <linux/clkdev.h>
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| 
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| struct clkops {
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| 	void			(*enable)(struct clk *);
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| 	void			(*disable)(struct clk *);
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| 	unsigned long		(*getrate)(struct clk *);
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| 	int			(*setrate)(struct clk *, unsigned long);
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| };
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| 
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| struct clk {
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| 	const struct clkops	*ops;
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| 
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| 	void __iomem	*clk_rst;	/* clock reset control register */
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| 	int		fnclksel;	/* functional clock select (APBC) */
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| 	uint32_t	enable_val;	/* value for clock enable (APMU) */
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| 	unsigned long	rate;
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| 	int		enabled;
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| };
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| 
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| extern struct clkops apbc_clk_ops;
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| extern struct clkops apmu_clk_ops;
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| 
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| #define APBC_CLK(_name, _reg, _fnclksel, _rate)			\
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| struct clk clk_##_name = {					\
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| 		.clk_rst	= APBC_##_reg,			\
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| 		.fnclksel	= _fnclksel,			\
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| 		.rate		= _rate,			\
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| 		.ops		= &apbc_clk_ops,		\
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| }
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| 
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| #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops)	\
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| struct clk clk_##_name = {					\
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| 		.clk_rst	= APBC_##_reg,			\
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| 		.fnclksel	= _fnclksel,			\
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| 		.rate		= _rate,			\
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| 		.ops		= _ops,				\
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| }
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| 
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| #define APMU_CLK(_name, _reg, _eval, _rate)			\
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| struct clk clk_##_name = {					\
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| 		.clk_rst	= APMU_##_reg,			\
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| 		.enable_val	= _eval,			\
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| 		.rate		= _rate,			\
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| 		.ops		= &apmu_clk_ops,		\
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| }
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| 
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| #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops)		\
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| struct clk clk_##_name = {					\
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| 		.clk_rst	= APMU_##_reg,			\
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| 		.enable_val	= _eval,			\
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| 		.rate		= _rate,			\
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| 		.ops		= _ops,				\
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| }
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| 
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| #define INIT_CLKREG(_clk, _devname, _conname)			\
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| 	{							\
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| 		.clk		= _clk,				\
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| 		.dev_id		= _devname,			\
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| 		.con_id		= _conname,			\
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| 	}
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| 
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| extern struct clk clk_pxa168_gpio;
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| extern struct clk clk_pxa168_timers;
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