6de714c21a
Make sure the RTC-interrupts are masked at boot by adding a new helper function to be used at SOC-init. This fixes hanged boot on all AT91 SOCs with an RTC (but RM9200), for example, after a reset during an RTC-update or if an RTC-alarm goes off after shutdown (e.g. when using RTC wakeup). The RTC and RTT-peripherals are powered by backup power (VDDBU) (on all AT91 SOCs but RM9200) and are not reset on wake-up, user, watchdog or software reset. This means that their interrupts may be enabled during early boot if, for example, they where not disabled during a previous shutdown (e.g. due to a buggy driver or a non-clean shutdown such as a user reset). Furthermore, an RTC or RTT-alarm may also be active. The RTC and RTT-interrupts use the shared system-interrupt line, which is also used by the PIT, and if an interrupt occurs before a handler (e.g. RTC-driver) has been installed this leads to the system interrupt being disabled and prevents the system from booting. Note that when boot hangs due to an early RTC or RTT-interrupt, the only way to get the system to start again is to remove the backup power (e.g. battery) or to disable the interrupt manually from the bootloader. In particular, a user reset is not sufficient. Signed-off-by: Johan Hovold <jhovold@gmail.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: stable@vger.kernel.org # 3.11.x
65 lines
2.3 KiB
C
65 lines
2.3 KiB
C
/*
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* SoC specific header file for the AT91SAM9N12
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*
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* Copyright (C) 2012 Atmel Corporation
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*
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* Common definitions, based on AT91SAM9N12 SoC datasheet
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*
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* Licensed under GPLv2 or later
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*/
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#ifndef _AT91SAM9N12_H_
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#define _AT91SAM9N12_H_
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
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#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
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#define AT91SAM9N12_ID_FUSE 4 /* FUSE Controller */
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#define AT91SAM9N12_ID_USART0 5 /* USART 0 */
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#define AT91SAM9N12_ID_USART1 6 /* USART 1 */
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#define AT91SAM9N12_ID_USART2 7 /* USART 2 */
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#define AT91SAM9N12_ID_USART3 8 /* USART 3 */
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#define AT91SAM9N12_ID_TWI0 9 /* Two-Wire Interface 0 */
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#define AT91SAM9N12_ID_TWI1 10 /* Two-Wire Interface 1 */
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#define AT91SAM9N12_ID_MCI 12 /* High Speed Multimedia Card Interface */
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#define AT91SAM9N12_ID_SPI0 13 /* Serial Peripheral Interface 0 */
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#define AT91SAM9N12_ID_SPI1 14 /* Serial Peripheral Interface 1 */
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#define AT91SAM9N12_ID_UART0 15 /* UART 0 */
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#define AT91SAM9N12_ID_UART1 16 /* UART 1 */
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#define AT91SAM9N12_ID_TCB 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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#define AT91SAM9N12_ID_PWM 18 /* Pulse Width Modulation Controller */
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#define AT91SAM9N12_ID_ADC 19 /* ADC Controller */
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#define AT91SAM9N12_ID_DMA 20 /* DMA Controller */
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#define AT91SAM9N12_ID_UHP 22 /* USB Host High Speed */
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#define AT91SAM9N12_ID_UDP 23 /* USB Device High Speed */
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#define AT91SAM9N12_ID_LCDC 25 /* LCD Controller */
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#define AT91SAM9N12_ID_ISI 25 /* Image Sensor Interface */
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#define AT91SAM9N12_ID_SSC 28 /* Synchronous Serial Controller */
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#define AT91SAM9N12_ID_TRNG 30 /* TRNG */
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#define AT91SAM9N12_ID_IRQ0 31 /* Advanced Interrupt Controller */
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/*
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* User Peripheral physical base addresses.
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*/
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#define AT91SAM9N12_BASE_USART0 0xf801c000
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#define AT91SAM9N12_BASE_USART1 0xf8020000
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#define AT91SAM9N12_BASE_USART2 0xf8024000
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#define AT91SAM9N12_BASE_USART3 0xf8028000
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/*
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* System Peripherals
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*/
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#define AT91SAM9N12_BASE_RTC 0xfffffeb0
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/*
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* Internal Memory.
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*/
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#define AT91SAM9N12_SRAM_BASE 0x00300000 /* Internal SRAM base address */
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#define AT91SAM9N12_SRAM_SIZE SZ_32K /* Internal SRAM size (32Kb) */
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#define AT91SAM9N12_ROM_BASE 0x00100000 /* Internal ROM base address */
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#define AT91SAM9N12_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
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#endif
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