582d5fbd4e
This patch adds the support for new PIO controller found on some at91sam SOCs. - more peripheral multiplexing - more features to configure on a PIO (pull-down, Schmitt trigger, debouncer) - support for several IRQ triggering features (type and polarity) Support for those new features are retrieved from the device tree compatibility string. Debugfs at91_gpio file is updated to monitor configuration. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
74 lines
3.4 KiB
C
74 lines
3.4 KiB
C
/*
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* arch/arm/mach-at91/include/mach/at91_pio.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Parallel I/O Controller (PIO) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_PIO_H
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#define AT91_PIO_H
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#define PIO_PER 0x00 /* Enable Register */
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#define PIO_PDR 0x04 /* Disable Register */
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#define PIO_PSR 0x08 /* Status Register */
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#define PIO_OER 0x10 /* Output Enable Register */
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#define PIO_ODR 0x14 /* Output Disable Register */
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#define PIO_OSR 0x18 /* Output Status Register */
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#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
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#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
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#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
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#define PIO_SODR 0x30 /* Set Output Data Register */
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#define PIO_CODR 0x34 /* Clear Output Data Register */
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#define PIO_ODSR 0x38 /* Output Data Status Register */
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#define PIO_PDSR 0x3c /* Pin Data Status Register */
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#define PIO_IER 0x40 /* Interrupt Enable Register */
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#define PIO_IDR 0x44 /* Interrupt Disable Register */
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#define PIO_IMR 0x48 /* Interrupt Mask Register */
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#define PIO_ISR 0x4c /* Interrupt Status Register */
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#define PIO_MDER 0x50 /* Multi-driver Enable Register */
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#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
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#define PIO_MDSR 0x58 /* Multi-driver Status Register */
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#define PIO_PUDR 0x60 /* Pull-up Disable Register */
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#define PIO_PUER 0x64 /* Pull-up Enable Register */
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#define PIO_PUSR 0x68 /* Pull-up Status Register */
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#define PIO_ASR 0x70 /* Peripheral A Select Register */
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#define PIO_ABCDSR1 0x70 /* Peripheral ABCD Select Register 1 [some sam9 only] */
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#define PIO_BSR 0x74 /* Peripheral B Select Register */
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#define PIO_ABCDSR2 0x74 /* Peripheral ABCD Select Register 2 [some sam9 only] */
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#define PIO_ABSR 0x78 /* AB Status Register */
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#define PIO_IFSCDR 0x80 /* Input Filter Slow Clock Disable Register */
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#define PIO_IFSCER 0x84 /* Input Filter Slow Clock Enable Register */
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#define PIO_IFSCSR 0x88 /* Input Filter Slow Clock Status Register */
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#define PIO_SCDR 0x8c /* Slow Clock Divider Debouncing Register */
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#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
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#define PIO_PPDDR 0x90 /* Pad Pull-down Disable Register */
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#define PIO_PPDER 0x94 /* Pad Pull-down Enable Register */
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#define PIO_PPDSR 0x98 /* Pad Pull-down Status Register */
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#define PIO_OWER 0xa0 /* Output Write Enable Register */
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#define PIO_OWDR 0xa4 /* Output Write Disable Register */
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#define PIO_OWSR 0xa8 /* Output Write Status Register */
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#define PIO_AIMER 0xb0 /* Additional Interrupt Modes Enable Register */
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#define PIO_AIMDR 0xb4 /* Additional Interrupt Modes Disable Register */
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#define PIO_AIMMR 0xb8 /* Additional Interrupt Modes Mask Register */
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#define PIO_ESR 0xc0 /* Edge Select Register */
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#define PIO_LSR 0xc4 /* Level Select Register */
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#define PIO_ELSR 0xc8 /* Edge/Level Status Register */
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#define PIO_FELLSR 0xd0 /* Falling Edge/Low Level Select Register */
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#define PIO_REHLSR 0xd4 /* Rising Edge/ High Level Select Register */
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#define PIO_FRLHSR 0xd8 /* Fall/Rise - Low/High Status Register */
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#define PIO_SCHMITT 0x100 /* Schmitt Trigger Register */
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#define ABCDSR_PERIPH_A 0x0
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#define ABCDSR_PERIPH_B 0x1
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#define ABCDSR_PERIPH_C 0x2
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#define ABCDSR_PERIPH_D 0x3
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#endif
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