71f349799b
At the moment we have a mixture of left-over version 0 and new-format version 1 files in arch/powerpc/boot/dts. This is potentially confusing to people new to the dts format attempting to figure it out. So, this patch converts all the as-yet unconverted dts v0 files and converts them to v1. They're mechanically-converted, and not hand tweaked so in some cases they're not 100% in keeping with usual v1 style, but the convertor program does have some heuristics so the discrepancies aren't too bad. I have checked that this patch produces no changes to the resulting dtb binaries. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: Geoff Levand <geoffrey.levand@am.sony.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
230 lines
5.5 KiB
Text
230 lines
5.5 KiB
Text
/*
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* Device Tree Source for EP405
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*
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* Copyright 2007 IBM Corp.
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* Benjamin Herrenschmidt <benh@kernel.crashing.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "ep405";
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compatible = "ep405";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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ethernet0 = &EMAC;
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serial0 = &UART0;
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serial1 = &UART1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,405GP";
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reg = <0x00000000>;
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clock-frequency = <200000000>; /* Filled in by zImage */
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timebase-frequency = <0>; /* Filled in by zImage */
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <16384>;
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d-cache-size = <16384>;
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000>; /* Filled in by zImage */
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};
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UIC0: interrupt-controller {
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compatible = "ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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plb {
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compatible = "ibm,plb3";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; /* Filled in by zImage */
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SDRAM0: memory-controller {
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compatible = "ibm,sdram-405gp";
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dcr-reg = <0x010 0x002>;
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};
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MAL: mcmal {
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compatible = "ibm,mcmal-405gp", "ibm,mcmal";
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <1>;
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num-rx-chans = <1>;
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interrupt-parent = <&UIC0>;
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interrupts = <
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0xb 0x4 /* TXEOB */
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0xc 0x4 /* RXEOB */
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0xa 0x4 /* SERR */
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0xd 0x4 /* TXDE */
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0xe 0x4 /* RXDE */>;
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};
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POB0: opb {
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compatible = "ibm,opb-405gp", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0xef600000 0xef600000 0x00a00000>;
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dcr-reg = <0x0a0 0x005>;
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clock-frequency = <0>; /* Filled in by zImage */
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UART0: serial@ef600300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600300 0x00000008>;
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virtual-reg = <0xef600300>;
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clock-frequency = <0>; /* Filled in by zImage */
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current-speed = <9600>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x0 0x4>;
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};
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UART1: serial@ef600400 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600400 0x00000008>;
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virtual-reg = <0xef600400>;
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clock-frequency = <0>; /* Filled in by zImage */
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current-speed = <9600>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x1 0x4>;
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};
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IIC: i2c@ef600500 {
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compatible = "ibm,iic-405gp", "ibm,iic";
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reg = <0xef600500 0x00000011>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x2 0x4>;
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};
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GPIO: gpio@ef600700 {
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compatible = "ibm,gpio-405gp";
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reg = <0xef600700 0x00000020>;
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};
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EMAC: ethernet@ef600800 {
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linux,network-index = <0x0>;
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device_type = "network";
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compatible = "ibm,emac-405gp", "ibm,emac";
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interrupt-parent = <&UIC0>;
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interrupts = <
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0xf 0x4 /* Ethernet */
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0x9 0x4 /* Ethernet Wake Up */>;
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local-mac-address = [000000000000]; /* Filled in by zImage */
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reg = <0xef600800 0x00000070>;
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mal-device = <&MAL>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <1500>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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phy-mode = "rmii";
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phy-map = <0x00000000>;
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};
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};
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EBC0: ebc {
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compatible = "ibm,ebc-405gp", "ibm,ebc";
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dcr-reg = <0x012 0x002>;
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#address-cells = <2>;
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#size-cells = <1>;
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/* The ranges property is supplied by the bootwrapper
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* and is based on the firmware's configuration of the
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* EBC bridge
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*/
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clock-frequency = <0>; /* Filled in by zImage */
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/* NVRAM and RTC */
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nvrtc@4,200000 {
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compatible = "ds1742";
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reg = <0x00000004 0x00200000 0x00000000>; /* size fixed up by zImage */
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};
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/* "BCSR" CPLD contains a PCI irq controller */
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bcsr@4,0 {
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compatible = "ep405-bcsr";
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reg = <0x00000004 0x00000000 0x00000010>;
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interrupt-controller;
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/* Routing table */
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irq-routing = [ 00 /* SYSERR */
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01 /* STTM */
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01 /* RTC */
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01 /* FENET */
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02 /* NB PCIIRQ mux ? */
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03 /* SB Winbond 8259 ? */
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04 /* Serial Ring */
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05 /* USB (ep405pc) */
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06 /* XIRQ 0 */
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06 /* XIRQ 1 */
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06 /* XIRQ 2 */
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06 /* XIRQ 3 */
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06 /* XIRQ 4 */
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06 /* XIRQ 5 */
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06 /* XIRQ 6 */
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07]; /* Reserved */
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};
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};
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PCI0: pci@ec000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
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primary;
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reg = <0xeec00000 0x00000008 /* Config space access */
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0xeed80000 0x00000004 /* IACK */
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0xeed80000 0x00000004 /* Special cycle */
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0xef480000 0x00000040>; /* Internal registers */
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed. Chip supports a second
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* IO range but we don't use it for now
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
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0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
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/* That's all I know about IRQs on that thing ... */
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interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
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interrupt-map = <
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/* USB */
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0x7000 0x0 0x0 0x0 &UIC0 0x1e 0x8 /* IRQ5 */
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>;
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};
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};
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chosen {
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linux,stdout-path = "/plb/opb/serial@ef600300";
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};
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};
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