 7034228792
			
		
	
	
	7034228792
	
	
	
		
			
			Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
		
			
				
	
	
		
			36 lines
		
	
	
	
		
			1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			36 lines
		
	
	
	
		
			1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
| #ifndef __ASM_RC32434_IRQ_H
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| #define __ASM_RC32434_IRQ_H
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| 
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| #define NR_IRQS 256
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| 
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| #include <asm/mach-generic/irq.h>
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| #include <asm/mach-rc32434/rb.h>
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| 
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| /* Interrupt Controller */
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| #define IC_GROUP0_PEND		(REGBASE + 0x38000)
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| #define IC_GROUP0_MASK		(REGBASE + 0x38008)
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| #define IC_GROUP_OFFSET		0x0C
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| 
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| #define NUM_INTR_GROUPS		5
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| 
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| /* 16550 UARTs */
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| #define GROUP0_IRQ_BASE		8	/* GRP2 IRQ numbers start here */
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| 					/* GRP3 IRQ numbers start here */
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| #define GROUP1_IRQ_BASE		(GROUP0_IRQ_BASE + 32)
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| 					/* GRP4 IRQ numbers start here */
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| #define GROUP2_IRQ_BASE		(GROUP1_IRQ_BASE + 32)
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| 					/* GRP5 IRQ numbers start here */
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| #define GROUP3_IRQ_BASE		(GROUP2_IRQ_BASE + 32)
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| #define GROUP4_IRQ_BASE		(GROUP3_IRQ_BASE + 32)
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| 
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| #define UART0_IRQ		(GROUP3_IRQ_BASE + 0)
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| 
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| #define ETH0_DMA_RX_IRQ		(GROUP1_IRQ_BASE + 0)
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| #define ETH0_DMA_TX_IRQ		(GROUP1_IRQ_BASE + 1)
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| #define ETH0_RX_OVR_IRQ		(GROUP3_IRQ_BASE + 9)
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| #define ETH0_TX_UND_IRQ		(GROUP3_IRQ_BASE + 10)
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| 
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| #define GPIO_MAPPED_IRQ_BASE	GROUP4_IRQ_BASE
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| #define GPIO_MAPPED_IRQ_GROUP	4
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| 
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| #endif	/* __ASM_RC32434_IRQ_H */
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